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Upload config & rtlil artefacts and add mcu_soc #138

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21 changes: 17 additions & 4 deletions .github/workflows/test-examples.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -23,17 +23,16 @@ jobs:
environment: ${{ vars.ENVIRONMENT }}
strategy:
matrix:
dry: [true, false]
repo:
- name: "ChipFlow/chipflow-examples"
design: "minimal"
- name: "ChipFlow/chipflow-examples"
design: "mcu_soc"
env:
DRY: ${{ matrix.dry && '--dry-run' || '' }}
is_dry: ${{ matrix.dry && '(dry run)' || '' }}
our_path: ${{ github.workspace}}
test_repo_path: "${{ github.workspace }}/${{ matrix.repo.name }}"

name: ${{ matrix.dry && 'Test Submit - Dry run' || 'Test submit' }}
name: 'Submit examples: ${{matrix.repo.design}}'

steps:
- name: Check out source code
Expand Down Expand Up @@ -101,6 +100,20 @@ jobs:
pdm run chipflow pin lock
pdm sim-check

- name: Submit build dry run
working-directory: ${{ env.test_repo_path }}/${{ matrix.repo.design }}
run: |
set -o pipefail
pdm run chipflow silicon submit --dry-run

- name: Upload build artefacts
uses: actions/upload-artifact@v4
with:
name: submit-artefacts-${{ matrix.repo.design }}
path: |
${{ env.test_repo_path }}/${{ matrix.repo.design }}/rtlil
${{ env.test_repo_path }}/${{ matrix.repo.design }}/config

- name: Submit build ${{ env.is_dry }}
working-directory: ${{ env.test_repo_path }}/${{ matrix.repo.design }}
run: |
Expand Down
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