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@robtaylor robtaylor commented Feb 12, 2025

Package Pin Interface

This PR implements a structured interface for determining package pins in ChipFlow.

Key Changes

  1. Added abstract methods to define standard pin types in package definitions:

    • Power and ground pins
    • Clock pins
    • Reset pins
    • JTAG pins
    • Heartbeat pins
  2. Implemented these methods in both package types:

    • BareDiePackageDef
    • QuadPackageDef
  3. Enhanced the Package class to:

    • Support new pin types
    • Initialize pins from package definitions
    • Support both legacy and new pin formats
  4. Added comprehensive tests in test_package_pins.py

  5. Created documentation in docs/package_pins.md

Backward Compatibility

The implementation maintains backward compatibility with the existing TOML configuration format while introducing a new, more flexible format.

Ready for Review

All tests are passing, and the implementation is ready for review.

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@property
@abc.abstractmethod
def heartbeat(self) -> Dict(int, Pin):
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The clock in some cases comes as two pins close to each other to be connected to XTAL.

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hmm, good point. Is that a config option to generate a oscillator?

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Currently we have nothing to specify use of XTAL, this needs to be added somehow.

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The clock in some cases comes as two pins close to each other to be connected to XTAL.

If you have external crystal you will need a crystal oscillator analog block on the chip. The actual clock will then be an output of this oscillator.

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What also can happen is that clock is delivered as differential signal; but this can also be for digital signals. Likely only to add when use case is there.

@robtaylor robtaylor linked an issue Feb 14, 2025 that may be closed by this pull request
@robtaylor robtaylor marked this pull request as ready for review March 18, 2025 13:28
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I've updated this PR to implement a complete interface for package pins as discussed.

Key enhancements:

  1. Implemented all abstract methods in both package types with sensible defaults
  2. Added support for new power pin format while maintaining backward compatibility
  3. Created comprehensive tests with 76% code coverage
  4. Added documentation explaining the new interface

All tests are passing. Ready for review!

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github-actions bot commented May 1, 2025

Tests Skipped Failures Errors Time
9 0 💤 0 ❌ 9 🔥 4.118s ⏱️

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Haven't looked through the tests yet, but these are my comments so far

core_jtag: JTAGPins

def to_set(self) -> Set[Pin]:
return {p for pp in self.core_power for p in asdict(pp).values()} | \
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what is the asdict doing here?

ret = []
for q in range(0,3):
ret.append(sorted(quadrants[q]))
return ret
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it's worth noting that this won't give pins in bonding pad order which might be relevant in some cases - this can only be determined on a pattern-by-package (or by custom design in the case of a substrate or RDL for a WLCSP package).

An example for the PGA144 we used for the previous tapeout is the table on page 3 of https://europractice-ic.com/wp-content/uploads/2019/06/CD_PGA144.pdf but this is always going to differ

@robtaylor robtaylor force-pushed the packagepins branch 9 times, most recently from 7d71c83 to 5fc63cf Compare July 2, 2025 10:06
@robtaylor robtaylor force-pushed the packagepins branch 3 times, most recently from 3ec99b5 to 203e0d6 Compare July 2, 2025 12:08
@robtaylor robtaylor changed the base branch from main to sim-common July 2, 2025 15:10
@robtaylor robtaylor force-pushed the packagepins branch 2 times, most recently from 2ceb202 to d63aa26 Compare July 3, 2025 10:40
Base automatically changed from sim-common to main July 11, 2025 17:20
@robtaylor robtaylor marked this pull request as draft July 12, 2025 15:31
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Has some WIP for better pin allocation.

This should become shell and padring aware

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Add power, clock, jtag and heartbeat pins to package definitions

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