Adjust the gauge & the VIA size to have square endings.

[jpc-lip6]

The decap_w1 still have DRC issues under magic, so I wasn't able to confirm the DRC.
Otherwise, with the latest Coriolis commits it should complete.

[FatsieFS]

Why do the enclosures have to be square ?
In #5 I now computed the enclosures so that the width of the metal generated by the via is the same as the routing gauge wire width in the routing direction. The other enclosure I still keep to the minimum one provided by the design rules. Is this enough ?
Problem with direct patches to these files is that these are auto-generated out of the design rules so such a patch will be overwritten the next time I generate the Coriolis files.

[jpc-lip6]

The enclosure of the VIA in the non-perpandicular direction should be so that the whole metal width is equal to the wire width in said metal in the non-preferred direction.

It is the VIA non-prefered extension size which is used to compute the space occupied by the segment at it's end.
So if it is smaller than the non-perpandicular wire half-size, either the router cannot complete or you get DRC
violation.

And my psycho-rigid self likes squares shapes, easier to visually debug.

I understand about non patching generated file, but I wanted to provide you with an example of what I did
patch. What would be your preferred way of communication for the next time?

[FatsieFS]

Reason I use minimal enclosure is to allow two contact next to each other. If I am remember correctly I compute the pitch of the perpendicular wire and the enclosure in such a way that you can have two via on different nets next to each other.

[FatsieFS]

I understand about non patching generated file, but I wanted to provide you with an example of what I did
patch. What would be your preferred way of communication for the next time?

It's fine, just wanted to explain why I did not apply the full patch as is.