Adding Number of Logic levels and number of timing graph levels to ti…#2383

behnam-rs wants to merge 2 commits intoverilog-to-routing:openfpgaverilog-to-routing/vtr-verilog-to-routing:openfpgafrom

behnam-rs:Logic_levelizerbehnam-rs/vtr-verilog-to-routing:Logic_levelizerCopy head branch name to clipboard