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Upgraded the solver in the AP flow to support a "Z" dimension representing the layer. This code only kicks on when the architecture has more than one layer, since in the single layer case there is no point to compute the Z dimension.

Upgraded the solver in the AP flow to support a "Z" dimension
representing the layer. This code only kicks on when the architecture
has more than one layer, since in the single layer case there is no
point to compute the Z dimension.
@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Sep 5, 2025
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LGTM, but a few comments embedded.
Should also add a before and after runtime etc. comparison on the 2D case.

// For multi-die FPGAs, we apply extra weight in the layer dimension
// since moving between layers tends to cost more wiring than moving
// within the same layer.
double multidie_net_w = wl_net_w * layer_distance_cost_fac_;
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How is this set? Ideally we'd set these as 1/wiring supply for each dimension. Note that x and y should have different factors too when the wiring supply in each dimension is different (e.g. S10, 7-series)


/// @brief For most FPGA architectures, the cost of moving horizontally is
/// equivalent to the cost moving vertically (i.e. moving in increasing
/// x-dimension has the same cost as moving the same amount in the
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Not true for S10 and 7-series (different wiring supplies). Also may not be true for timing in many architectures.

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Should be able to get these cost factors from some Soheil/Amin code in the annealer (they compute prefix sums of wiring supply in each dimension; should be able to ask for total wiring in x or y or z from them.

// (other than the first iteration). These are stored to be used as anchor
// blocks during the solver.
vtr::vector<APBlockId, double> block_x_locs_legalized;
vtr::vector<APBlockId, double> block_y_locs_legalized;
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Probably want to say that for speed, the various _z values are ignored / not updated or used if a device has only one die.

<add_atom name_pattern="out:p_45" />
</partition>
<partition name="p_48">
<add_region subtile="-1" layer_low="1" layer_high="1" x_low="9" x_high="9" y_low="8" y_high="8" />
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Do you want all the IOs on layer 1? Or would it be a stronger test if there were some on each layer?

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For this specific example, the IOs are only located on layer 1 and the CLBs are located on layer 0. This is a simple test architecture to just ensure that different blocks are placed on different layers.

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