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[Place][InitT] Changed Default Init T Estimator to Equilibrium #3294

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e1496c4
[Place][InitT] Changed Default Init T Estimator to Equilibrium
AlexandreSinger Oct 6, 2025
0a3c1f2
[Place][InitT] Updated On-Merge Golden Results
AlexandreSinger Oct 6, 2025
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2 changes: 1 addition & 1 deletion doc/src/vpr/command_line_usage.rst
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Expand Up @@ -850,7 +850,7 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe
* ``cost_variance``: Estimates the initial temperature using the variance of cost after a set of trial swaps. The initial temperature is set to a value proportional to the variance.
* ``equilibrium``: Estimates the initial temperature by trying to predict the equilibrium temperature for the initial placement (i.e. the temperature that would result in no change in cost).

**Default** ``cost_variance``
**Default** ``equilibrium``

.. option:: --init_t <float>

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2 changes: 1 addition & 1 deletion vpr/src/base/read_options.cpp
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Expand Up @@ -2323,7 +2323,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
"\tequilibrium: Estimates the initial temperature by trying to "
"predict the equilibrium temperature for the initial placement "
"(i.e. the temperature that would result in no change in cost).")
.default_value("cost_variance")
.default_value("equilibrium")
.show_in(argparse::ShowIn::HELP_ONLY);

place_grp.add_argument(args.PlaceInitT, "--init_t")
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6 changes: 3 additions & 3 deletions ...sks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt
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@@ -1,3 +1,3 @@
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.91 vpr 62.53 MiB -1 -1 0.10 16916 1 0.05 -1 -1 32024 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64032 6 1 13 14 2 8 9 4 4 16 clb auto 23.8 MiB 0.01 22 27 6 15 6 62.5 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.8829e-05 2.8382e-05 0.000261465 0.000217889 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00235757 0.00212728 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00170712 0.00164334
k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.93 vpr 62.57 MiB -1 -1 0.14 17260 1 0.06 -1 -1 31980 -1 -1 2 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64076 3 -1 23 23 2 3 5 4 4 16 clb auto 23.8 MiB 0.01 3 12 2 3 7 62.6 MiB 0.00 0.00 0.620297 -7.93119 -0.620297 0.545 0.01 6.0445e-05 5.1078e-05 0.000540631 0.00048682 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00313926 0.00293123 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00237872 0.0022794
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.47 vpr 67.04 MiB -1 -1 0.08 27956 1 0.03 -1 -1 35908 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock 68648 6 1 13 14 2 8 9 4 4 16 clb auto 28.4 MiB 0.00 23 18 450 161 197 92 67.0 MiB 0.00 0.00 1.02737 1.02737 -3.59667 -1.02737 0.545 0.01 2.2386e-05 1.7505e-05 0.00141611 0.00109159 -1 -1 -1 -1 20 11 11 107788 107788 10441.3 652.579 0.01 0.00277003 0.00227007 742 1670 -1 13 3 10 10 137 80 1.2939 0.545 -4.03651 -1.2939 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00106682 0.000989623
k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.51 vpr 66.91 MiB -1 -1 0.09 28592 1 0.04 -1 -1 35576 -1 -1 2 3 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock 68520 3 -1 23 23 2 3 5 4 4 16 clb auto 28.3 MiB 0.01 5 3 12 4 2 6 66.9 MiB 0.00 0.00 0.620233 0.620297 -7.93119 -0.620297 0.545 0.01 6.0765e-05 5.1182e-05 0.000423486 0.000375079 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00215853 0.00198452 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00156675 0.00148493
6 changes: 3 additions & 3 deletions ...s/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt
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@@ -1,3 +1,3 @@
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.12 vpr 61.70 MiB -1 -1 0.11 16536 1 0.08 -1 -1 31596 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63184 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.7 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.8582e-05 2.7966e-05 0.000277936 0.000219445 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.02 0.00248443 0.00222718 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00178059 0.00171145
k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.12 vpr 61.63 MiB -1 -1 0.15 16580 1 0.06 -1 -1 31648 -1 -1 1 2 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63112 2 -1 16 16 1 2 3 3 3 9 -1 auto 23.2 MiB 0.01 3 6 4 0 2 61.6 MiB 0.00 0.00 0.545 -3.815 -0.545 0.545 0.00 4.1349e-05 3.4027e-05 0.000423997 0.000380122 -1 -1 -1 -1 2 1 1 53894 53894 1178.84 130.982 0.00 0.00258339 0.00244324 283 309 -1 1 1 1 1 8 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00225406 0.00217221
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.56 vpr 66.72 MiB -1 -1 0.09 27956 1 0.04 -1 -1 35668 -1 -1 2 6 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock 68324 6 1 13 14 2 8 9 4 4 16 clb auto 28.1 MiB 0.00 23 18 450 161 197 92 66.7 MiB 0.00 0.00 1.02737 1.02737 -3.59667 -1.02737 0.545 0.01 2.2666e-05 1.781e-05 0.00197092 0.00153227 -1 -1 -1 -1 20 11 11 107788 107788 10441.3 652.579 0.01 0.00365711 0.00291454 742 1670 -1 13 3 10 10 137 80 1.2939 0.545 -4.03651 -1.2939 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00105744 0.000982198
k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.59 vpr 66.92 MiB -1 -1 0.10 28208 1 0.04 -1 -1 35676 -1 -1 1 2 0 0 success v8.0.0-14013-ge1496c441d-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:51:15 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock 68524 2 -1 16 16 1 2 3 3 3 9 -1 auto 28.4 MiB 0.01 3 3 6 4 0 2 66.9 MiB 0.00 0.00 0.603526 0.603526 -4.0491 -0.603526 0.603526 0.00 3.8014e-05 3.1187e-05 0.000340609 0.000305195 -1 -1 -1 -1 2 1 1 53894 53894 1178.84 130.982 0.00 0.00168803 0.00155817 283 309 -1 1 1 1 1 8 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00165916 0.00159042
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