Add intrinsics for the new FP conversions introduced by the 2024 dpISA

[amilendra]

FEAT_FPRCVT adds 4 new variants for each FCVTAS, FCVTAU, FCVTMS, FCVTMU, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTZS, and FCVTZU instruction. 1) Half Precision to 32-bit
2) Half Precision to 64-bit
3) Single Precision to 64-bit
4) Double Precision to 32-bit

For the Single Precision to 64-bit and Double Precision to 32-bit variants, this patch adds two new intrinsics, that reduce to

• Single Precision to 64-bit : Dd,Sn
• Double Precision to 32-bit : Sd,Dn

The intrinsics for conversions from Half Precision are already defined. However they are documented as reducing to the incorrect instruction format; Hd,Hn, so this patch fixes them to be

• Half Precision to 32-bit : Sd,Hn
• Half Precision to 64-bit : Dd,Hn

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[ktkachov]

As these instructions operate only on scalar values should they be defined in the arm_acle.h header instead of arm_neon.h?

[CarolineConcatto]

Hi @ktkachov,
So this is a PR to add in the ACLE specification more type sizes to intrinsics, they are also using converts between only neon registers. There is no general purpose registers.
I am not sure why you are asking which library should this be on? But just in case from the ACLE what should be in

<arm_acle.h> provides access to intrinsics that do not belong
to the more specific header files below. These intrinsics are in the
C implementation namespace and begin with double underscores. It is
unspecified whether they are available without the header being
included. When __ARM_ACLE is defined to 1, the header file is
guaranteed to be available.

The new type for the converts are for FPRCVT.
These new instructions will probably be inside arm_neon.h, as I think the previous ones are also in

[Lukacma]

Is there a reason you didn't include GPR variants here ?

[amilendra]

My reasoning was that the fact that there were no existing conversion intrinsics that lowered to GPRs (https://developer.arm.com/documentation/ddi0602/2025-06/SIMD-FP-Instructions/FCVTZS--scalar--integer---Floating-point-convert-to-signed-integer--rounding-toward-zero--scalar--) we would only need to implement the intrinsics that lower to Neon registers. Thinking a bit more I guess it is better to extend the proposal to intrinsics that lower to both GP and Neon registers?

[Lukacma]

LGTM