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@amilendra amilendra commented Aug 20, 2025

FEAT_FPRCVT adds 4 new variants for each FCVTAS, FCVTAU, FCVTMS, FCVTMU, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTZS, and FCVTZU instruction. 1) Half Precision to 32-bit
2) Half Precision to 64-bit
3) Single Precision to 64-bit
4) Double Precision to 32-bit

For the Single Precision to 64-bit and Double Precision to 32-bit variants, this patch adds two new intrinsics, that reduce to

  • Single Precision to 64-bit : Dd,Sn
  • Double Precision to 32-bit : Sd,Dn

The intrinsics for conversions from Half Precision are already defined. However they are documented as reducing to the incorrect instruction format; Hd,Hn, so this patch fixes them to be

  • Half Precision to 32-bit : Sd,Hn
  • Half Precision to 64-bit : Dd,Hn

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@amilendra amilendra force-pushed the 2025-acle-fprcvt branch 2 times, most recently from 4dbaa35 to a4bc412 Compare September 15, 2025 11:56
@ktkachov
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As these instructions operate only on scalar values should they be defined in the arm_acle.h header instead of arm_neon.h?

@CarolineConcatto
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Hi @ktkachov,
So this is a PR to add in the ACLE specification more type sizes to intrinsics, they are also using converts between only neon registers. There is no general purpose registers.
I am not sure why you are asking which library should this be on? But just in case from the ACLE what should be in

<arm_acle.h> provides access to intrinsics that do not belong
to the more specific header files below. These intrinsics are in the
C implementation namespace and begin with double underscores. It is
unspecified whether they are available without the header being
included. When __ARM_ACLE is defined to 1, the header file is
guaranteed to be available.

The new type for the converts are for FPRCVT.
These new instructions will probably be inside arm_neon.h, as I think the previous ones are also in

FEAT_FPRCVT adds 4 new variants for each FCVTAS, FCVTAU, FCVTMS, FCVTMU,
FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTZS, and FCVTZU instruction.
1) Half Precision to 32-bit
2) Half Precision to 64-bit
3) Single Precision to 64-bit
4) Double Precision to 32-bit

For the Single Precision to 64-bit and Double Precision to 32-bit variants,
this patch adds two new intrinsics, that reduce to
- Single Precision to 64-bit : <INST> Dd,Sn
- Double Precision to 32-bit : <INST> Sd,Dn

The intrinsics for conversions from Half Precision are already defined.
However they are documented as reducing to the incorrect instruction format;
<INST> Hd,Hn, so this patch fixes them to be
- Half Precision to 32-bit   : <INST> Sd,Hn
- Half Precision to 64-bit   : <INST> Dd,Hn
uint32x2_t vcvta_u32_f32(float32x2_t a) a -> Vn.2S FCVTAU Vd.2S,Vn.2S Vd.2S -> result A32/A64
uint32x4_t vcvtaq_u32_f32(float32x4_t a) a -> Vn.4S FCVTAU Vd.4S,Vn.4S Vd.4S -> result A32/A64
int32_t vcvts_s32_f32(float32_t a) a -> Sn FCVTZS Sd,Sn Sd -> result A64
int64_t vcvts_s64_f32(float32_t a) a -> Sn FCVTZS Dd,Sn Dd -> result A64
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Is there a reason you didn't include GPR variants here ?

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My reasoning was that the fact that there were no existing conversion intrinsics that lowered to GPRs (https://developer.arm.com/documentation/ddi0602/2025-06/SIMD-FP-Instructions/FCVTZS--scalar--integer---Floating-point-convert-to-signed-integer--rounding-toward-zero--scalar--) we would only need to implement the intrinsics that lower to Neon registers. Thinking a bit more I guess it is better to extend the proposal to intrinsics that lower to both GP and Neon registers?

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LGTM

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4 participants