Add FPGA Timer/CountDownTimer feature #1
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| end else begin | ||
| counter <= count_down_value; | ||
| end | ||
| end else begin |
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| end else begin | |
| end else begin |
Wrong indentation.
rtl/timer.v
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| // Timer module | ||
| // | ||
| // This module counts elapsed time or perform the delay |
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| // This module counts elapsed time or perform the delay | |
| // This module counts elapsed time or performs the delay |
rtl/timer.v
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| end | ||
| end else begin | ||
| if (mode == MODE_TIMER) begin | ||
| if (enable == 1'b1) begin |
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Current code increments the counter whenever the enable pin is high. This is OK, however I'd like to see a setting that would modify this behavior so the measurement would stop on the first falling edge. This way we could choose to measure the sum of enable high states or just the first pulse.
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Starting CI. |
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@mprse Can we proceed to unblock Mbed OS PR ? |
@fkjagodzinski Are you happy with the last changes? |
What changes? Nothing has changed since my review. |
I added the requested option, to count only the first pulse.
Even with this one is merged. PR ARMmbed/mbed-os#11147 will have to wait for the FPGA-test-shield firmware version update and this is planned next year I think. |
Dang, that is far way. We shall close 11147 and keep in opened in jira as internal ticket with branch available to continue this work the next year? |
| if (mode == MODE_TIMER) begin | ||
| if (enable == 1'b1 && count_once_reg == 1'b1) begin | ||
| counter <= counter + 1; | ||
| end | ||
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| if (count_once == 1'b1 && negedge_enable == 1'b1) begin | ||
| count_once_reg <= 1'b0; | ||
| end |
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I found the count_once_reg name a bit misleading as I assumed a not-inverted logic here. Consider renaming to something like counting_enabled.
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This PR adds Verilog implementation for FPGA Timer which can be used in two modes:
The accuracy of the FPGA Timer is 10 ns: 1 timer tick corresponds to 10 ns.
The mbed OS part of the PR:
ARMmbed/mbed-os#11147