Description
In _sfdp_set_quad_enabled(), sr_write_size is fixed to QSPI_MAX_STATUS_REGISTER_SIZE (0x03). I found this causing issue while porting QSPI for CY8CPROTO_062_4343W to work with the NOR flash S25FL512S. For this flash chip, the write size for the status register must be 2. Otherwise, enabling quad mode fails.
Reference: S25FL512S datasheet, Section: 9.3.7 Write Registers (WRR 01h). The following line makes it clear that write size must be 2.
CS# must be driven to the logic high state after the eighth or sixteenth bit of data has been latched. If not, the Write Registers (WRR) command is not executed.
Issue request type
[ ] Question
[X] Enhancement
[ ] Bug