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TARGET_STM32F7: Reset QSPI in default mode on abort for all versions. #10343

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Merged
merged 1 commit into from
Apr 9, 2019
Merged

TARGET_STM32F7: Reset QSPI in default mode on abort for all versions. #10343

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2 changes: 0 additions & 2 deletions targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9668,8 +9668,6 @@ typedef struct
/* QUADSPI */
/* */
/******************************************************************************/
/* QUADSPI IP version */
#define QSPI1_V1_0
/***************** Bit definition for QUADSPI_CR register *******************/
#define QUADSPI_CR_EN_Pos (0U)
#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
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2 changes: 0 additions & 2 deletions targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f756xx.h
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Expand Up @@ -9937,8 +9937,6 @@ typedef struct
/* QUADSPI */
/* */
/******************************************************************************/
/* QUADSPI IP version */
#define QSPI1_V1_0
/***************** Bit definition for QUADSPI_CR register *******************/
#define QUADSPI_CR_EN_Pos (0U)
#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
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23 changes: 12 additions & 11 deletions targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.c
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Expand Up @@ -490,10 +490,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
__HAL_DMA_DISABLE(hqspi->hdma);
}

#if defined(QSPI1_V1_0)
/* Clear Busy bit */
/* MBED, see #10049 */
/* Clear Busy bit */
HAL_QSPI_Abort_IT(hqspi);
#endif

/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
Expand Down Expand Up @@ -529,10 +528,10 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
}
}
#if defined(QSPI1_V1_0)

/* MBED, see #10049 */
/* Workaround - Extra data written in the FIFO at the end of a read transfer */
HAL_QSPI_Abort_IT(hqspi);
#endif /* QSPI_V1_0*/

/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
Expand Down Expand Up @@ -879,11 +878,10 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
{
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
#if defined(QSPI1_V1_0)

/* MBED, see #10049 */
/* Clear Busy bit */
status = HAL_QSPI_Abort(hqspi);
#endif /* QSPI_V1_0 */
}
}

Expand Down Expand Up @@ -968,11 +966,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
{
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
#if defined(QSPI1_V1_0)

/* MBED, see #10049 */
/* Workaround - Extra data written in the FIFO at the end of a read transfer */
status = HAL_QSPI_Abort(hqspi);
#endif /* QSPI_V1_0 */
}
}

Expand Down Expand Up @@ -1921,6 +1918,10 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)

if (status == HAL_OK)
{
/* MBED, see #10049 */
/* Reset functional mode configuration to indirect write mode by default */
CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);

/* Update state */
hqspi->State = HAL_QSPI_STATE_READY;
}
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