Add CC3220SF LAUNCHXL to Mbed OS

TESTS/mbed_hal/lp_ticker/main.cpp

@@ -107,7 +107,7 @@ void lp_ticker_info_test()
 
     TEST_ASSERT(p_ticker_info->frequency >= 4000);
     TEST_ASSERT(p_ticker_info->frequency <= 64000);
-    TEST_ASSERT(p_ticker_info->bits >= 12);
+    TEST_ASSERT(p_ticker_info->bits >= 12 && p_ticker_info->bits <= 32);
 }
 
 #if DEVICE_SLEEP

TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp

@@ -55,7 +55,7 @@ void spi_async_handler()
 {
     int event = spi_irq_handler_asynch(&spi);
 
-    if (event == SPI_EVENT_COMPLETE) {
+    if (event & SPI_EVENT_COMPLETE) {
         async_trasfer_done = true;
     }
 }
@@ -136,7 +136,7 @@ void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPI
 
             async_trasfer_done = false;
 
-            spi_master_transfer(&spi, tx_buf, TRANSFER_COUNT, rx_buf, TRANSFER_COUNT, 8, (uint32_t)spi_async_handler, 0, DMA_USAGE_NEVER);
+            spi_master_transfer(&spi, tx_buf, TRANSFER_COUNT, rx_buf, TRANSFER_COUNT, 8, (uint32_t)spi_async_handler, SPI_EVENT_COMPLETE, DMA_USAGE_NEVER);
             while (!async_trasfer_done);
 
             for (int i = 0; i < TRANSFER_COUNT; i++) {

components/storage/blockdevice/COMPONENT_SD/mbed_lib.json

@@ -165,6 +165,12 @@
             "SPI_MISO": "D12",
             "SPI_CLK": "D13",
             "SPI_CS": "D10"
+        },
+        "CC3220SF_LAUNCHXL": {
+            "SPI_MOSI": "D11",
+            "SPI_MISO": "D12",
+            "SPI_CLK": "D13",
+            "SPI_CS": "D10"
         }
     }
 }

targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralPins.h

@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+/************GPIO***************/
+extern const PinMap PinMap_GPIO[];
+
+/************PWM****************/
+extern const PinMap PinMap_PWM[];
+
+/************UART***************/
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+extern const PinMap PinMap_UART_CTS[];
+extern const PinMap PinMap_UART_RTS[];
+
+#endif

targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PortNames.h

@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0,
+    Port1 = 1,
+    Port2 = 2,
+    Port3 = 3
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c

@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2016-2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== CC3220SF_LAUNCHXL.c ========
+ *  This file is responsible for setting up the board specific items for the
+ *  CC3220SF_LAUNCHXL board.
+ */
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include <ti/devices/cc32xx/inc/hw_ints.h>
+#include <ti/devices/cc32xx/inc/hw_memmap.h>
+#include <ti/devices/cc32xx/inc/hw_types.h>
+
+#include <ti/devices/cc32xx/driverlib/rom.h>
+#include <ti/devices/cc32xx/driverlib/rom_map.h>
+#include <ti/devices/cc32xx/driverlib/adc.h>
+#include <ti/devices/cc32xx/driverlib/gpio.h>
+#include <ti/devices/cc32xx/driverlib/pin.h>
+#include <ti/devices/cc32xx/driverlib/prcm.h>
+#include <ti/devices/cc32xx/driverlib/ti_spi_driverlib.h>
+#include <ti/devices/cc32xx/driverlib/sdhost.h>
+#include <ti/devices/cc32xx/driverlib/ti_timer.h>
+#include <ti/devices/cc32xx/driverlib/uart.h>
+#include <ti/devices/cc32xx/driverlib/udma.h>
+#include <ti/devices/cc32xx/driverlib/interrupt.h>
+#include <ti/devices/cc32xx/driverlib/wdt.h>
+
+#include <ti/drivers/Power.h>
+#include <ti/drivers/power/PowerCC32XX.h>
+
+#include "CC3220SF_LAUNCHXL.h"
+
+/*
+ *  =============================== Power ===============================
+ */
+/*
+ * This table defines the parking state to be set for each parkable pin
+ * during LPDS. (Device pins must be parked during LPDS to achieve maximum
+ * power savings.)  If the pin should be left unparked, specify the state
+ * PowerCC32XX_DONT_PARK.  For example, for a UART TX pin, the device
+ * will automatically park the pin in a high state during transition to LPDS,
+ * so the Power Manager does not need to explictly park the pin.  So the
+ * corresponding entries in this table should indicate PowerCC32XX_DONT_PARK.
+ */
+PowerCC32XX_ParkInfo parkInfo[] = {
+/*          PIN                    PARK STATE              PIN ALIAS (FUNCTION)
+     -----------------  ------------------------------     -------------------- */
+    {PowerCC32XX_PIN01, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO10              */
+    {PowerCC32XX_PIN02, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO11              */
+    {PowerCC32XX_PIN03, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO12              */
+    {PowerCC32XX_PIN04, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO13              */
+    {PowerCC32XX_PIN05, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO14              */
+    {PowerCC32XX_PIN06, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO15              */
+    {PowerCC32XX_PIN07, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO16              */
+    {PowerCC32XX_PIN08, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO17              */
+    {PowerCC32XX_PIN13, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* FLASH_SPI_DIN       */
+    {PowerCC32XX_PIN15, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO22              */
+    {PowerCC32XX_PIN16, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDI (JTAG DEBUG)    */
+    {PowerCC32XX_PIN17, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDO (JTAG DEBUG)    */
+    {PowerCC32XX_PIN19, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TCK (JTAG DEBUG)    */
+    {PowerCC32XX_PIN20, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TMS (JTAG DEBUG)    */
+    {PowerCC32XX_PIN18, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO28              */
+    {PowerCC32XX_PIN21, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* SOP2                */
+    {PowerCC32XX_PIN29, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL1             */
+    {PowerCC32XX_PIN30, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL2             */
+    {PowerCC32XX_PIN45, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* DCDC_ANA2_SW_P      */
+    {PowerCC32XX_PIN50, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO0               */
+    {PowerCC32XX_PIN52, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* RTC_XTAL_N          */
+    {PowerCC32XX_PIN53, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO30              */
+    {PowerCC32XX_PIN55, PowerCC32XX_WEAK_PULL_UP_STD},   /* GPIO1 (XDS_UART_RX) */
+    {PowerCC32XX_PIN57, PowerCC32XX_WEAK_PULL_UP_STD},   /* GPIO2 (XDS_UART_TX) */
+    {PowerCC32XX_PIN58, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO3               */
+    {PowerCC32XX_PIN59, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO4               */
+    {PowerCC32XX_PIN60, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO5               */
+    {PowerCC32XX_PIN61, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO6               */
+    {PowerCC32XX_PIN62, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO7               */
+    {PowerCC32XX_PIN63, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO8               */
+    {PowerCC32XX_PIN64, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO9               */
+};
+
+/*
+ *  This structure defines the configuration for the Power Manager.
+ *
+ *  In this configuration the Power policy is disabled by default (because
+ *  enablePolicy is set to false).  The Power policy can be enabled dynamically
+ *  at runtime by calling Power_enablePolicy(), or at build time, by changing
+ *  enablePolicy to true in this structure.
+ */
+const PowerCC32XX_ConfigV1 PowerCC32XX_config = {
+    .policyInitFxn = &PowerCC32XX_initPolicy,
+    .policyFxn = &PowerCC32XX_sleepPolicy,
+    .enterLPDSHookFxn = NULL,
+    .resumeLPDSHookFxn = NULL,
+    .enablePolicy = false,
+    .enableGPIOWakeupLPDS = true,
+    .enableGPIOWakeupShutdown = true,
+    .enableNetworkWakeupLPDS = true,
+    .wakeupGPIOSourceLPDS = PRCM_LPDS_GPIO13,
+    .wakeupGPIOTypeLPDS = PRCM_LPDS_FALL_EDGE,
+    .wakeupGPIOFxnLPDS = NULL,
+    .wakeupGPIOFxnLPDSArg = 0,
+    .wakeupGPIOSourceShutdown = PRCM_HIB_GPIO13,
+    .wakeupGPIOTypeShutdown = PRCM_HIB_RISE_EDGE,
+    .ramRetentionMaskLPDS = PRCM_SRAM_COL_1 | PRCM_SRAM_COL_2 |
+        PRCM_SRAM_COL_3 | PRCM_SRAM_COL_4,
+    .keepDebugActiveDuringLPDS = false,
+    .ioRetentionShutdown = PRCM_IO_RET_GRP_1,
+    .pinParkDefs = parkInfo,
+    .numPins = sizeof(parkInfo) / sizeof(PowerCC32XX_ParkInfo)
+};
+/*
+ *  =============================== SPI ===============================
+ */
+#include <ti/drivers/ti_SPI.h>
+#include <ti/drivers/spi/SPICC32XXDMA.h>
+
+SPICC32XXDMA_Object spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPICOUNT];
+
+#ifdef TOOLCHAIN_GCC_ARM
+__attribute__ ((aligned (32)))
+#elif defined TOOLCHAIN_ARM
+__attribute__ ((aligned (32)))
+#elif defined TOOLCHAIN_IAR
+#pragma data_alignment=32
+#endif
+uint32_t spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPICOUNT];
+
+const SPICC32XXDMA_HWAttrsV1 spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPICOUNT] = {
+    /* index 0 is reserved for LSPI that links to the NWP */
+    {
+        .baseAddr = LSPI_BASE,
+        .intNum = INT_LSPI,
+        .intPriority = (~0),
+        .spiPRCM = PRCM_LSPI,
+        .csControl = SPI_SW_CTRL_CS,
+        .csPolarity = SPI_CS_ACTIVEHIGH,
+        .pinMode = SPI_4PIN_MODE,
+        .turboMode = SPI_TURBO_OFF,
+        .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI0],
+        .defaultTxBufValue = 0,
+        .rxChannelIndex = UDMA_CH12_LSPI_RX,
+        .txChannelIndex = UDMA_CH13_LSPI_TX,
+        .minDmaTransferSize = 100,
+        .mosiPin = SPICC32XXDMA_PIN_NO_CONFIG,
+        .misoPin = SPICC32XXDMA_PIN_NO_CONFIG,
+        .clkPin = SPICC32XXDMA_PIN_NO_CONFIG,
+        .csPin = SPICC32XXDMA_PIN_NO_CONFIG
+    },
+    {
+        .baseAddr = GSPI_BASE,
+        .intNum = INT_GSPI,
+        .intPriority = (~0),
+        .spiPRCM = PRCM_GSPI,
+        .csControl = SPI_HW_CTRL_CS,
+        .csPolarity = SPI_CS_ACTIVELOW,
+        .pinMode = SPI_4PIN_MODE,
+        .turboMode = SPI_TURBO_OFF,
+        .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI1],
+        .defaultTxBufValue = 0,
+        .rxChannelIndex = UDMA_CH6_GSPI_RX,
+        .txChannelIndex = UDMA_CH7_GSPI_TX,
+        .minDmaTransferSize = 10,
+        .mosiPin = SPICC32XXDMA_PIN_07_MOSI,
+        .misoPin = SPICC32XXDMA_PIN_06_MISO,
+        .clkPin = SPICC32XXDMA_PIN_05_CLK,
+        .csPin = SPICC32XXDMA_PIN_08_CS
+    }
+};
+
+const SPI_Config SPI_config[CC3220SF_LAUNCHXL_SPICOUNT] = {
+    {
+        .fxnTablePtr = &SPICC32XXDMA_fxnTable,
+        .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI0],
+        .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI0]
+    },
+    {
+        .fxnTablePtr = &SPICC32XXDMA_fxnTable,
+        .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI1],
+        .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI1]
+    }
+};
+
+const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT;
+
+/*
+ *  =============================== DMA ===============================
+ */
+#include <ti/drivers/dma/UDMACC32XX.h>
+
+#if defined(__TI_COMPILER_VERSION__)
+#pragma DATA_ALIGN(dmaControlTable, 1024)
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma data_alignment=1024
+#elif defined(__GNUC__)
+__attribute__ ((aligned (1024)))
+#endif
+static tDMAControlTable dmaControlTable[64];
+
+/*
+ *  ======== dmaErrorFxn ========
+ *  This is the handler for the uDMA error interrupt.
+ */
+static void dmaErrorFxn(uintptr_t arg)
+{
+    int status = MAP_uDMAErrorStatusGet();
+    MAP_uDMAErrorStatusClear();
+
+    /* Suppress unused variable warning */
+    (void)status;
+
+    while (1);
+}
+
+UDMACC32XX_Object udmaCC3220SObject;
+
+const UDMACC32XX_HWAttrs udmaCC3220SHWAttrs = {
+    .controlBaseAddr = (void *)dmaControlTable,
+    .dmaErrorFxn = (UDMACC32XX_ErrorFxn)dmaErrorFxn,
+    .intNum = INT_UDMAERR,
+    .intPriority = (~0)
+};
+
+const UDMACC32XX_Config UDMACC32XX_config = {
+    .object = &udmaCC3220SObject,
+    .hwAttrs = &udmaCC3220SHWAttrs
+};
+/*
+ *  =============================== General ===============================
+ */
+/*
+ *  ======== CC3220SF_LAUNCHXL_initGeneral ========
+ */
+void CC3220SF_LAUNCHXL_initGeneral(void)
+{
+    MAP_IntMasterEnable();
+    //MAP_IntEnable(FAULT_SYSTICK);
+    PRCMCC3200MCUInit();
+    //Power_init();
+}
+
+#if defined TOOLCHAIN_ARM
+__attribute__((section("signature_section")))
+#elif defined TOOLCHAIN_IAR
+#pragma default_variable_attributes = @ ".dbghdr"
+#elif defined TOOLCHAIN_GCC_ARM
+__attribute__ ((section (".dbghdr")))
+#endif
+const unsigned long ulDebugHeader[]=
+{
+                0x5AA5A55A,
+                0x000FF800,
+                0xEFA3247D
+};