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FPGA CI shield: Add a watchdog timing test #11433
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@fkjagodzinski, thank you for your changes. |
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Please review |
Ping |
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@mprse, @maciejbocianski, @jamesbeyond we are still awaiting review on this , could you please take a look asap? |
mprse
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The test is okay, but I think we should decide:
- where to put the timing tests,
- do we want to remove old tests (which use host pc to count elapsed time)
The same problem I have here: PR #11147.
Currently, all FPGA tests are in the following location:
TESTS\mbed_hal_fpga_ci_test_shield
I'm not sure if this is a good idea to put alternative timing tests in the same location together with peripheral fpga tests. My proposition is to create an additional folder for the timing tests. Something like:
TESTS\mbed_timing_fpga_ci_test_shield.
Alternatively, we may also break the current convention and add FPGA tests close too non-FPGA versions:
TESTS\mbedmicro-rtos-mbed\basic
TESTS\mbedmicro-rtos-mbed\basic_fpga.
I think we should not remove the original tests since they might be valuable to users who do not have FPGA shields. On CI we may run only one test version depending if FPGA is supported for the board.
Use the FPGA IOMetrics feature to verify the watchdog timeout accuracy.
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Ok, I rebased this patch to current master (079564b) and removed the last commit that deleted the original, non-FPGA test. Regarding the test location -- I do not have a strong opinion about this as long all FPGA tests have the string |
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I think put FPGA timing related test into one folder would ideal. |
Create a directory for all timing tests that make use of the FPGA shield, regardless of the component they test. Move the FPGA-Watchdog-timing test.
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@jamesbeyond, @mprse, I moved the test to a new directory. The full test suite name is now |
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Please review Lets run one CI meanwhile |
Test run: FAILEDSummary: 1 of 5 test jobs failed Failed test jobs:
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Watchdog test failed, please review |
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Turns out the failures are pretty straight forward to explain this time. :) Because this new test suite was moved to a new dir (as requested above), it has to be filtered out in the CI until we provide the FPGA shields. From the logs I can tell we have a filter with |
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@fkjagodzinski Please update when you can |
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@0xc0170 Good to have this test. Do you plan to merge it? |
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Yes @yarbcy this requires a minor update. Will take care of this shortly. |
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https://github.com/ARMmbed/mbed-os-ci/pull/1084 should fix the greentea failures on the CI. |
The aforementioned CI update is still pending so we can't take this yet. |
Integrated, will restart CI |
Test run: SUCCESSSummary: 5 of 5 test jobs passed |
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Please review |
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Test LGTM Regarding FPGA test placement I think that creating another folder for timing FPGA tests For me ideal would be to have fpga and non-fpga tests in the same place. In the near future FPGA shield become inherent part of test infrastructure and having the same functionality tests gathered in one place will make life easier.
What do you think @jamesbeyond @fkjagodzinski @mprse |
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As I said earlier, I don't have a strong opinion about the dir structure. I like your proposal @maciejbocianski. 👍 Isn't this a topic for a new PR though? This would require to move all the tests that make use of the FPGA shield. @jamesbeyond, @mprse shall I keep the current timing-specific dir, or revert to the original location? |
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I believe restructure would be a new PR.
As soon as this is decided, this PR is ready for integration, isn't it? |
Yep, correct. |
I think we can keep the test as it is in the |
Test run: SUCCESSSummary: 5 of 5 test jobs passed |
Description
Replace the
tests-mbed_hal-watchdog_timingwithtests-mbed_hal_fpga_ci_test_shield-watchdog_timingtests-mbed_timing_fpga_ci_test_shield-watchdog.The timeout measurement from the original test is based on heartbeat messages sent to a host PC via the greentea serial. This method is fairly inaccurate because the last timestamp received by the host will always be before the expected reset time. Thanks to
IOMetricsfeature of our new FPGA CI test shield, the watchdog timeout measurement boils down to counting the falling edges of the heartbeat signal. The pin used to output this signal is added to a list of restricted pins. This guarantees that no other signals (i.e. FPGA control) will interfere.Pull request type
Reviewers
@mprse, @maciejbocianski, @jamesbeyond
Release Notes