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@gatecat gatecat commented Sep 29, 2025

Allow attaching binary data from a custom software step (etc) to a sim model

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Tests Skipped Failures Errors Time
49 11 💤 0 ❌ 0 🔥 1.824s ⏱️

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github-actions bot commented Sep 29, 2025

PR Preview Action v1.6.2
Preview removed because the pull request was closed.
2025-10-09 07:44 UTC

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gatecat commented Oct 6, 2025

@robtaylor - ping?

@gatecat gatecat merged commit 5280d73 into main Oct 9, 2025
5 of 6 checks passed
@gatecat gatecat deleted the add-verilog-example branch October 9, 2025 07:42
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2 participants