LLVM assertion on ARM #21926
Description
Triggered by the following code on ARM with an optimization level no less than -O1.
function expm1_2(zr)
wr = isfinite(zr) ? zr - 2.0 : cos(zr)
Complex(wr)
end
# code_llvm(STDOUT, expm1_2, Tuple{Float32}, false, true)
expm1_2(1f0)The assertion is
julia-debug: /home/yuyichao/projects/julia/tests/master/deps/srccache/llvm-4.0.0/lib/CodeGen/VirtRegMap.cpp:443: void {anonymous}::VirtRegRewriter::rewrite(): Assertion `PhysReg && "Invalid SubReg for physical register"' failed.
And the MachineInstr this fails on is %D16<def> = COPY %vreg29:ssub_0<kill>; DPR:%vreg29.
And the enclosing block is
(udb) p MBBI->print(dbgs(), Indexes)
400B BB#1: derived from LLVM BB %if
Live Ins: %R4 %R5 %R8 %R9 %S16
Predecessors according to CFG: BB#0
416B %D16<def> = FCONSTD 128, pred:14, pred:%noreg; dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
432B %D17<def> = VCVTDS %S16<kill>, pred:14, pred:%noreg; dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
448B %D16<def> = VADDD %D17<kill>, %D16<kill>, pred:14, pred:%noreg; dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
464B %R10<def>, %R7<def> = VMOVRRD %D16, pred:14, pred:%noreg; dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
480B %R0<def> = MOVi 1, pred:14, pred:%noreg, opt:%noreg
512B %D16<def> = COPY %vreg29:ssub_0<kill>; DPR:%vreg29
560B B <BB#4>; dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
Successors according to CFG: BB#4(?%)
Before calling rewrite it's
BB#1: derived from LLVM BB %if
Live Ins: %R4 %R5 %R8 %R9 %S16
Predecessors according to CFG: BB#0
%vreg27<def> = FCONSTD 128, pred:14, pred:%noreg; DPR:%vreg27 dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
%vreg28<def> = VCVTDS %vreg17<kill>, pred:14, pred:%noreg; DPR:%vreg28 SPR:%vreg17 dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
%vreg29<def> = VADDD %vreg28<kill>, %vreg27<kill>, pred:14, pred:%noreg; DPR:%vreg29,%vreg28,%vreg27 dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
%vreg6<def>, %vreg5<def> = VMOVRRD %vreg29, pred:14, pred:%noreg; GPR:%vreg6,%vreg5 DPR:%vreg29 dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
%vreg72<def> = MOVi 1, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg72
%vreg67<def> = COPY %vreg29:ssub_0<kill>; DPR:%vreg67,%vreg29
B <BB#4>; dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
Successors according to CFG: BB#4(?%)
Not sure if this is already invalid.
Full machine IR before entering this pass is here
Full regalloc log is at here
This is likely a LLVM bug but I'm not able to reproduce with LLC so far....