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@lowsfer lowsfer commented Aug 21, 2025

Summary by CodeRabbit

  • Bug Fixes
    • Improved numerical stability in row-wise computations by adjusting initialization threshold to reduce overflow/underflow risk.
  • Refactor
    • Tuned GPU kernel launch constraints in latency-optimized builds to adjust occupancy without changing external behavior.
  • Documentation
    • Added detailed comments explaining exponentiation optimization and stability considerations.
  • Debugging
    • Added conditional runtime logging of per-head row statistics in debug builds to aid troubleshooting.

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📝 Walkthrough

Walkthrough

Refines kernel launch bounds under an NDEBUG/OPTIMIZE_FOR_LATENCY path, adds gated debug prints for XV GEMM row statistics, and reduces a numerical sentinel constant (safeInitRowMax) with explanatory comments. No public APIs or signatures changed.

Changes

Cohort / File(s) Summary
Kernel launch bounds and debug instrumentation
cpp/kernels/xqa/mha_sm90.cu
Under NDEBUG with OPTIMIZE_FOR_LATENCY, changes kernel_mha's launch_bounds to a single-parameter (__launch_bounds__(128 * 3)), removing the maxBlocksPerSM constraint in that branch. Adds conditional debug prints of rowMax and rowSum (gated by block/thread checks) in the XV GEMM path followed by a barrier. No API/signature changes.
Utility constant and documentation
cpp/kernels/xqa/utils.cuh
Changes safeInitRowMax from -1e+30F to -1e+5F and adds commentary explaining exp(x-rowMax) optimization and numerical stability rationale for the smaller sentinel. No API/signature changes.

Sequence Diagram(s)

(omitted)

Estimated code review effort

🎯 3 (Moderate) | ⏱️ ~20 minutes

Possibly related PRs

Suggested reviewers

  • jhaotingc

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Reviewing files that changed from the base of the PR and between 859eef3 and 28dc2d6.

📒 Files selected for processing (2)
  • cpp/kernels/xqa/mha_sm90.cu (2 hunks)
  • cpp/kernels/xqa/utils.cuh (1 hunks)
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  • cpp/kernels/xqa/mha_sm90.cu
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@lowsfer lowsfer enabled auto-merge (squash) August 21, 2025 06:56
@lowsfer lowsfer requested a review from jhaotingc August 21, 2025 06:57
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Actionable comments posted: 0

🧹 Nitpick comments (6)
cpp/kernels/xqa/utils.cuh (3)

32-36: Tighten literal type and fix comment typo (‘log2d’ → ‘log2e’).

  • log2e is declared as float but initialized with a double literal; add the F suffix to avoid implicit narrowing.
  • The comment uses log2d, which is a typo and can confuse readers.

Apply this diff:

-inline constexpr float log2e = 1.4426950408889634; // std::log2(M_E)
+inline constexpr float log2e = 1.4426950408889634F; // std::log2(M_E)
-/*  bias = rowMax * log2d  // shared for the whole row
+/*  bias = rowMax * log2e  // shared for the whole row
     exp(x-rowMax) = exp(x * log2e - bias)
 */

37-39: Value change to safeInitRowMax: good intent; suggest naming and documentation tweak.

Lowering the magnitude to -1e5F aligns with the stability note and should reduce FMA-induced issues. To match the guidelines (“Constants use kPREFIXED_UPPER_SNAKE”), keep the existing name for ABI/back-compat but introduce a named constant.

Apply this diff:

-// this reason, don't set a huge safeInitRowMax.
-inline constexpr float safeInitRowMax = -1e+5F;
+// This optimization can be numerically unstable when (x * log2e - bias) is fused into an FMA for large |x|.
+// To mitigate, avoid an excessively large sentinel for initialization.
+inline constexpr float kSAFE_INIT_ROW_MAX = -1e5F;
+inline constexpr float safeInitRowMax = kSAFE_INIT_ROW_MAX; // Backward-compatible alias.

Optionally, add a one-liner explaining the selection rationale, e.g., “Chosen to be far below plausible QK logits while avoiding extreme products with log2e.”


2116-2139: Avoid FMA fusion in softmax exponent to further improve stability.

Current form elem = exp2f(elem * log2e - bias) invites FMA. Pre-subtract then multiply to prevent fusion and lower catastrophic cancellation risk, while maintaining perf. Same change applies to both SWAP_AB and non-SWAP_AB variants.

Apply this diff for both warpGrpOnlineSoftmax() overloads:

-            float const maxVal = colMax[n][j];
-            float const bias = maxVal * log2e;
+            float const maxVal = colMax[n][j];
             ...
-                    float& elem = acc(m, n)(i, j);
-                    assert(maxVal >= elem);
-                    elem = exp2f(elem * log2e - bias);
+                    float& elem = acc(m, n)(i, j);
+                    assert(maxVal >= elem);
+                    float const delta = elem - maxVal;
+                    elem = exp2f(delta * log2e);

And similarly in the row-wise variant:

-            float const maxVal = rowMax[m][i];
-            float const bias = maxVal * log2e;
+            float const maxVal = rowMax[m][i];
             ...
-                    float& elem = acc(m, n)(i, j);
-                    assert(maxVal >= elem);
-                    elem = exp2f(elem * log2e - bias);
+                    float& elem = acc(m, n)(i, j);
+                    assert(maxVal >= elem);
+                    float const delta = elem - maxVal;
+                    elem = exp2f(delta * log2e);

Also applies to: 2440-2463

cpp/kernels/xqa/mha_sm90.cu (3)

1094-1110: Debug prints for non-SWAP_AB row stats: looks good; minor gate suggestion.

Gating on blockIdx.y == 1 and threadIdx.x == 0 keeps noise down and the barrier maintains ordering. Consider switching to blockIdx.y == 0 to ensure a print even when nbSubSeq == 1; or add a short comment explaining why y == 1 is preferred.


2950-2954: Optional: clamp normalization denominator to avoid division by tiny sums in corner cases.

Extremely adversarial inputs could yield near-zero sums before adding attention sinks. A tiny clamp protects against denorm/Inf without impacting normal runs.

Example:

-    auto const regOutScale = __frcp_rn(regColSum) * xvoScale;
+    auto const regOutScale = __frcp_rn(max(regColSum, Vec<float, decltype(regColSum)::size>::filled(1e-20f))) * xvoScale;

Same consideration applies to the row-wise variant.


840-846: Request targeted validation for NaN/Inf eradication on SPEC_DEC.

Given the PR goal, please run a stress A/B on SPEC_DEC with adversarial logits to confirm NaN/Inf are gone and that the safeInitRowMax tweak plus current exponent path holds.

If helpful, I can craft a focused harness that:

  • Forces all-masked rows and very negative tiles to check softmax behavior.
  • Sweeps large-magnitude pre-softmax values to check for NaN/Inf and overflow in exp2f paths.

Also applies to: 1094-1110

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📒 Files selected for processing (2)
  • cpp/kernels/xqa/mha_sm90.cu (2 hunks)
  • cpp/kernels/xqa/utils.cuh (1 hunks)
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🔇 Additional comments (2)
cpp/kernels/xqa/mha_sm90.cu (2)

832-836: Sanity: reinit of per-CTA maxima with new sentinel is consistent across passes.

Initializing gemm0CurrentSeqMax and gemm1AccColMax with the updated sentinel aligns the two-stage softmax flow. Good.

Also applies to: 1014-1019


633-637: Verify occupancy impact under OPTIMIZE_FOR_LATENCY and eliminate magic numbers

I wasn’t able to capture ptxas register/SMEM stats in this environment, so please run the following locally to ensure we don’t regress throughput on mid-/long-sequence shapes and to avoid hard-coding 128 * 3:

• File: cpp/kernels/xqa/mha_sm90.cu
• Lines: ~633–637

Apply this diff:

-    __launch_bounds__(128 * 3, headElems* ctaNbQHeads <= 128 * 16 ? 3 : 2)
+    __launch_bounds__(warp_size * gmmaWarpsPerGrp * 3, headElems * ctaNbQHeads <= 128 * 16 ? 3 : 2)
 #else
-    __launch_bounds__(128 * 3)
+    __launch_bounds__(warp_size * gmmaWarpsPerGrp * 3)

Then locally compile with ptxas statistics enabled:

nvcc -std=c++17 -O3 -DNDEBUG -DOPTIMIZE_FOR_LATENCY=1 -arch=sm_90 \
  -Xptxas -v -c cpp/kernels/xqa/mha_sm90.cu -o /dev/null 2>&1 | tee ptxas.txt

grep -E "ptxas info.*Used" ptxas.txt

Verify:

  • Registers per thread
  • Shared memory usage
  • Achieved occupancy (max resident warps/SM)

across representative sequence lengths and batch sizes to confirm no regression in latency‐optimized builds.

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lowsfer commented Aug 21, 2025

/bot run

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lowsfer commented Aug 21, 2025

/bot run

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PR_Github #16031 [ run ] triggered by Bot

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PR_Github #16035 [ run ] triggered by Bot

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PR_Github #16031 [ run ] completed with state ABORTED

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PR_Github #16035 [ run ] completed with state SUCCESS
/LLM/main/L0_MergeRequest_PR pipeline #12056 completed with status: 'FAILURE'

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lowsfer commented Aug 22, 2025

/bot run

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PR_Github #16094 [ run ] triggered by Bot

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PR_Github #16094 [ run ] completed with state SUCCESS
/LLM/main/L0_MergeRequest_PR pipeline #12103 completed with status: 'FAILURE'

symphonylyh pushed a commit to symphonylyh/TensorRT-LLM that referenced this pull request Aug 26, 2025
…VIDIA#6282 NVIDIA#6279

* [None][infra] Pin the version for triton to 3.3.1 (NVIDIA#6508)

Signed-off-by: qqiao <[email protected]>

* [None][infra] Pin the version for triton to 3.3.1 (NVIDIA#6508) (NVIDIA#6519) (NVIDIA#6549)

Signed-off-by: Yanchao Lu <[email protected]>

* [fix]: use safeInitRowMax instead of fp32_lowest to avoid NaN (NVIDIA#7087)

Signed-off-by: Yao Yao <[email protected]>

* [None][fix] Fix a numerical stability issue for XQA with spec dec

Signed-off-by: Yao Yao <[email protected]>

* fix typo

Signed-off-by: Jhao-Ting Chen <[email protected]>

* fix precompiled multi_query_token kernel not having is_fp8_out hash key (NVIDIA#6279)

Signed-off-by: Jhao-Ting Chen <[email protected]>

* [fix] Fix missing fields in xqa kernel cache key (NVIDIA#6282)

Signed-off-by: Yao Yao <[email protected]>

---------

Signed-off-by: qqiao <[email protected]>
Signed-off-by: Yanchao Lu <[email protected]>
Signed-off-by: Yao Yao <[email protected]>
Signed-off-by: Jhao-Ting Chen <[email protected]>
Co-authored-by: Emma Qiao <[email protected]>
Co-authored-by: Yanchao Lu <[email protected]>
Co-authored-by: Yao Yao <[email protected]>
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lowsfer commented Sep 3, 2025

/bot run

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PR_Github #17471 [ run ] triggered by Bot

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PR_Github #17471 [ run ] completed with state SUCCESS
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/bot run --disable-fail-fast

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PR_Github #17561 [ run ] triggered by Bot

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PR_Github #17561 [ run ] completed with state SUCCESS
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@lowsfer lowsfer merged commit c1aa7f3 into NVIDIA:main Sep 4, 2025
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greg-kwasniewski1 pushed a commit to nv-auto-deploy/TensorRT-LLM that referenced this pull request Sep 4, 2025
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