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1. master-slave-bus-address-router master-slave-bus-address-router Public

   A Verilog-based bus routing module that connects one master to multiple slaves using address-based decoding logic. Includes a modular SystemVerilog testbench (driver, monitor, scoreboard, etc.) to …

   SystemVerilog 1

2. seq-fulladder-modular-tb seq-fulladder-modular-tb Public

   Verilog RTL design for a full adder implemented sequentially useing half adders and an or gate on verilog, and a modular testbench (structured with a generator, driver, monitor, scoreboard) in Syst…

   SystemVerilog 1