[TIR] Extend DP4A tensor intrin #16293
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vincentccc
commented
Dec 29, 2023
vincentccc
commented
- Update u8s8s32 s8u8s32 u8u8u32
vinx13
reviewed
Jan 2, 2024
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| #if !defined(__CUDACC_RTC__) && defined(__CUDA_ARCH__) | ||
| __SM_61_INTRINSICS_DECL__ int __dp4a(unsigned int srcA, int srcB, int c) { | ||
| int ret; | ||
| asm volatile ("dp4a.u32.s32 %0, %1, %2, %3;" : "=r"(ret) : "r"(srcA), "r"(srcB), "r"(c)); | ||
| return ret; | ||
| } | ||
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| __SM_61_INTRINSICS_DECL__ int __dp4a(int srcA, unsigned int srcB, int c) { | ||
| int ret; | ||
| asm volatile ("dp4a.s32.u32 %0, %1, %2, %3;" : "=r"(ret) : "r"(srcA), "r"(srcB), "r"(c)); | ||
| return ret; | ||
| } | ||
| #endif /* !__CUDACC_RTC__ && defined(__CUDA_ARCH__) */ |
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these definitions are similar to sm_61_intrinsics.hpp, is there a reason to include them here?
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This is because the sm_61_intrinsics.hpp exclude s8xu8 and u8xs8 case
vinx13
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Jan 5, 2024
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