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This PR fixes an issue in the dlight GeMV rule and the low-batch GeMV rule. The issue happens when the inner spatial loop has small length (e.g., in the MoE gate layer, this length is usually 8).

The error is because the GeMV scheduling does not make sure that each TIR block reads/writes the same number of local registers, and this inconsistency leads to wrong generated code. For example, in the schedule (prior to this fix), the first TIR block was scheduled to assign each thread 2 local registers, while the second block was scheduled to assign each thread 1 local register, which is incorrect. Unfortunately, this error only shows up when the spatial loop has small length.

One regression test is added.

This PR fixes an issue in the dlight GeMV rule and the low-batch
GeMV rule. The issue happens when the inner spatial loop has small
length (e.g., in the MoE gate layer, this length is usually 8).

The error is because the GeMV scheduling does not make sure that
each TIR block reads/writes the same number of local registers,
and this inconsistency leads to wrong generated code. For example,
in the schedule (prior to this fix), the first TIR block was
scheduled to assign each thread 2 local registers, while the second
block was scheduled to assign each thread 1 local register, which
is incorrect. Unfortunately, this error only shows up when the
spatial loop has small length.

One regression test is added.
@MasterJH5574 MasterJH5574 force-pushed the tvm-dev/2024-03-23-gemv-register branch from 072991e to 1af0a03 Compare March 24, 2024 00:20
@tqchen tqchen merged commit 80bcf4c into apache:main Mar 24, 2024
thaisacs pushed a commit to thaisacs/tvm that referenced this pull request Apr 3, 2024
This PR fixes an issue in the dlight GeMV rule and the low-batch
GeMV rule. The issue happens when the inner spatial loop has small
length (e.g., in the MoE gate layer, this length is usually 8).

The error is because the GeMV scheduling does not make sure that
each TIR block reads/writes the same number of local registers,
and this inconsistency leads to wrong generated code. For example,
in the schedule (prior to this fix), the first TIR block was
scheduled to assign each thread 2 local registers, while the second
block was scheduled to assign each thread 1 local register, which
is incorrect. Unfortunately, this error only shows up when the
spatial loop has small length.

One regression test is added.
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2 participants