[VERILOG] VPI RAM controler to access python memory. #72

tqchen · 2017-03-16T00:12:19Z

No description provided.

tmoreau89 · 2017-03-16T06:07:44Z

verilog/tvm_vpi_ram.v

+// Usage: create and pass instance to additional arguments of $tvm_session.
+// Then  it will be automatically hook up the RAM logic.
+//
+module tvm_vpi_ram


For the tvm_vpi_ram module I would probably not use the 'in'/'out'/'ctrl' prefixes

tmoreau89 · 2017-03-16T06:08:03Z

verilog/tvm_vpi_ram.v

+module tvm_vpi_ram
+  # ( parameter READ_WIDTH = 8,
+      parameter WRITE_WIDTH = 8
+      )


We should add more parameters (see below)

tmoreau89 · 2017-03-16T06:08:32Z

verilog/tvm_vpi_ram.v

+      )
+   ( clk,
+     rst,
+     in_read_dequeue,


tmoreau89 · 2017-03-16T06:08:41Z

verilog/tvm_vpi_ram.v

+   ( clk,
+     rst,
+     in_read_dequeue,
+     in_write_enable,


tmoreau89

Overall this looks good - I made some suggestions on the verilog module input/output and parameter list (I'll point you to my buffer implementation tomorrow)

tmoreau89 · 2017-03-16T06:09:01Z

verilog/tvm_vpi_ram.v

+     in_read_dequeue,
+     in_write_enable,
+     in_write_data,
+     ctrl_read_req,


tmoreau89 · 2017-03-16T06:09:39Z

verilog/tvm_vpi_ram.v

+     in_write_data,
+     ctrl_read_req,
+     ctrl_read_addr,
+     ctrl_read_size,


I think that this should be a parameter instead of an input (mostly for performance reasons, we can discuss this tomorrow)

tmoreau89 · 2017-03-16T06:10:23Z

verilog/tvm_vpi_ram.v

+     ctrl_read_req,
+     ctrl_read_addr,
+     ctrl_read_size,
+     ctrl_write_req,


tmoreau89 · 2017-03-16T06:11:18Z

verilog/tvm_vpi_ram.v

+     ctrl_write_addr,
+     ctrl_write_size,
+     out_read_data,
+     out_read_valid,


not sure if this 'read_valid' signal is needed since the validity of the read is really determined by the module that consumes the data (and also produces the read address the cycle before)

I am thinking of a scenario where the module only takes charge of hook up the data, and simply connect it to next generalized FIFO, where such signal will be helpful

tmoreau89 · 2017-03-16T06:12:11Z

verilog/tvm_vpi_ram.v

+     ctrl_write_size,
+     out_read_data,
+     out_read_valid,
+     out_write_full


Instead of write full, we should have full and empty signals, and also a counter would be useful (counts the number of elements currently stored in the buffer)

There are two queues actually in this RAM module, one for read, and another one for the write, are you suggesting we need to have two signals, like

read_pending and write_pending?

tmoreau89 · 2017-03-16T06:12:46Z

verilog/tvm_vpi_ram.v

+   input in_write_enable;
+   input [WRITE_WIDTH-1:0] in_write_data;
+   input                   ctrl_read_req;
+   input [31:0]            ctrl_read_addr;


This should be parameterizable (instead of set to 32) since we can benefit from narrower address widths in order to optimize for timing closure.

* init * fix lint * update task_lint * more lint * more lint * lint * jenkinsfile * jenkinsfile * run relax only tests * python3.7 for pytest * point to personal ci-cpu docker * docker pull * test * fix cmake config * update * update * rebase * rebase

…er (apache#76) * [CI] Set up CI; format and lint relax code to pass CI (apache#72) * init * fix lint * update task_lint * more lint * more lint * lint * jenkinsfile * jenkinsfile * run relax only tests * python3.7 for pytest * point to personal ci-cpu docker * docker pull * test * fix cmake config * update * update * rebase * rebase * AutoTIR integration (apache#58) * [WIP] Basic task extraction mechanism is implemented. * [WIP] For gradual integration with Relay pipeline, meta_schedule/integration.py is created for relax to avoid potential conflict. * support tir tuning and injection mode * Add target field for Relax Extracted Task * 1. Create relax namespace/tvm objects/... for metaschedule to preserve relay support. 2. Promote target field from Optional<Target> to Target * Support ApplyHistoryBest * Reflect feedback from Yuchen * minor improvement and fix linter issue * add ASF header * Reorganize file structure * fix lint errors * remove the import-outside-toplevel * Reflect comments * remove redundant comment * As per discussion w/ Yuchen, ApplyHistoryBest is introduced as a Relax transformation pass. * remove redundant print msg * fix lint * reflect comments * Yuchen's change * relax ConstantNode in parser and printer * Add constant data in the metasection * rebase * Support ir_module(metadata=json_str) * update test case * remove print info * Update tests * clang-format * pylint * fix ci * Save a copy of metadata in RelaxTransformer * Fix comments * fix comments Co-authored-by: Yuchen Jin <[email protected]> Co-authored-by: Sunghyun Park <[email protected]>