GitHub - ashutosh321607/8-bit-RISC-processor-verilog: A 8 bit RISC Processor implemented in Verilog HDL and simulated in Vivado.

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A 8 bit RISC Processor implemented in Verilog HDL and simulated in Vivado.

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Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
end_game		end_game
CONTRIBUTING.md		CONTRIBUTING.md
Music_Genre_Classification.ipynb		Music_Genre_Classification.ipynb
Music_genre_classification_NN.ipynb		Music_genre_classification_NN.ipynb

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Kumari Rani

Design the ram module
Design the Alu module
Design the simulation File

Abhishek Shingane

Design the Control Unit module with the help of Ashutosh garg and Kumari rani
Design the pc module
Design the main module

Ashutosh garg

Design the Clock_div module
Design the Seven_segment module
Design the reg module
Write the Constrains file