Share more of the TYP_MASK handling and support rewriting TYP_MASK operands in rationalization #103288
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…erands in rationalization
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| if (varTypeIsMask(operand->TypeGet())) | ||
| { | ||
| #if defined(FEATURE_HW_INTRINSICS) |
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Instead wrap the if-condition in #ifdef FEATURE_MASKED_HW_INTRINSICS
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TYP_MASK and a lot of the surrounding support isn't under that feature switch.
If we were to centralize everything under that feature switch, I think it should be a separate PR. However, I'm also not convinced we need that as we didn't set any such flag up for XARCH.
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Have a separate PR is fine for me, but do we even see TYP_MASK if it is not FEATURED_HW_INTRINSICS?
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I don't believe we do today, but that doesn't mean it will never happen. varTypeIsMask returns constant false on unsupported platforms, so this just ensures any future scenarios handle this appropriately and will be optimized out as dead code otherwise.
| CorInfoType simdBaseJitType, | ||
| unsigned simdSize) | ||
| { | ||
| assert(varTypeIsMask(type)); |
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Do we need to pass a TYP_MASK for type every time we call gtNewSimdCvtVectorToMaskNode ? Since we only have one TYP_MASK, feels like we could just get rid of this parameter.
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It's here to support any future expansion desired. For example, it may be important to differentiate mask based on size.
src/coreclr/jit/hwintrinsic.cpp
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| if (!varTypeIsMask(op2)) | ||
| { | ||
| retNode->AsHWIntrinsic()->Op(2) = gtNewSimdCvtVectorToMaskNode(retType, op2, simdBaseJitType, simdSize); | ||
| retNode->AsHWIntrinsic()->Op(2) = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op2, simdBaseJitType, simdSize); |
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probably add an assert in gtNewSimdCvtVectorToMaskNode() that type == TYP_MASK?
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That assert already exists and is what caught the failure.
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This resolves the issue introduced by #102702 which was discovered in #103094 (comment).
The bug was missed in the initial PR as the Arm64 handling for
mask <-> vectorconversions was a bit different from Xarch, and it wasn't expected to be able to encounter nodes in such a shape.