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[RISC-V] Add pseudo instruction not and replace xori when immediate is -1 #117967

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Merged
merged 3 commits into from
Aug 4, 2025
Merged

[RISC-V] Add pseudo instruction not and replace xori when immediate is -1 #117967

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9c4d0af
[RISC-V] Add pseudo instruction not
credo-quia-absurdum Jul 22, 2025
99ff2b5
[RISC-V] emit not
credo-quia-absurdum Jul 22, 2025
0285c4a
[RISC-V] Replace xori with not when immediate is -1
credo-quia-absurdum Jul 22, 2025
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4 changes: 2 additions & 2 deletions src/coreclr/jit/codegenriscv64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1009,7 +1009,7 @@ void CodeGen::genCodeForIncSaturate(GenTree* tree)
GetEmitter()->emitIns_R_R_I(INS_addi, attr, targetReg, operandReg, 1);
// bne targetReg, zero, 2 * 4
GetEmitter()->emitIns_R_R_I(INS_bne, attr, targetReg, REG_R0, 8);
GetEmitter()->emitIns_R_R_I(INS_xori, attr, targetReg, targetReg, -1);
GetEmitter()->emitIns_R_R(INS_not, attr, targetReg, targetReg);

genProduceReg(tree);
}
Expand Down Expand Up @@ -1691,7 +1691,7 @@ void CodeGen::genCodeForNegNot(GenTree* tree)
else if (tree->OperIs(GT_NOT))
{
assert(!varTypeIsFloating(targetType));
GetEmitter()->emitIns_R_R_I(INS_xori, attr, targetReg, operandReg, -1);
GetEmitter()->emitIns_R_R(INS_not, attr, targetReg, operandReg);
}

genProduceReg(tree);
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2 changes: 1 addition & 1 deletion src/coreclr/jit/emitriscv64.cpp
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Expand Up @@ -650,7 +650,7 @@ void emitter::emitIns_R_R(
{
code_t code = emitInsCode(ins);

if (INS_mov == ins || INS_sext_w == ins || (INS_clz <= ins && ins <= INS_rev8))
if (INS_mov == ins || INS_sext_w == ins || INS_not == ins || (INS_clz <= ins && ins <= INS_rev8))
{
assert(isGeneralRegisterOrR0(reg1));
assert(isGeneralRegisterOrR0(reg2));
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1 change: 1 addition & 0 deletions src/coreclr/jit/instrsriscv64.h
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Expand Up @@ -37,6 +37,7 @@ INST(nop, "nop", 0, 0x00000013)
//// R_R
INST(mov, "mv", 0, 0x00000013)
INST(sext_w, "sext.w", 0, 0x0000001b)
INST(not, "not", 0, 0xFFF04013)

////R_I
INST(lui, "lui", 0, 0x00000037)
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