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Fix bug for Assertion failed '(op3Reg != targetReg) || (op1Reg == targetReg)' during 'Generate code' #62343

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Fix bug for Assertion failed '(op3Reg != targetReg) || (op1Reg == targetReg)' during 'Generate code' #62343

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17 changes: 13 additions & 4 deletions src/coreclr/jit/hwintrinsiccodegenxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2097,16 +2097,25 @@ void CodeGen::genFMAIntrinsic(GenTreeHWIntrinsic* node)
}
else
{
// targetReg could be op1NodeReg, op2NodeReg, or not equal to any op
// op1 = (op1 * op2) + [op3] or op2 = (op1 * op2) + [op3]
// ? = (op1 * op2) + [op3] or ? = (op1 * op2) + op3
// 213 form: XMM1 = (XMM2 * XMM1) + [XMM3]
// targetReg could be op1NodeReg, op2NodeReg, op3NodeReg or not equal to any op
// op3 may or may not be isContained or isUsedFromSpillTemp, no extra work for both case
// op1/op2/op3/? = (op1 * op2) + [op3] or ? = (op1 * op2) + op3
if (!copiesUpperBits && (targetReg == op2NodeReg))
{
// op2 = (op1 * op2) + [op3]
// 213 form: XMM1 = (XMM2 * XMM1) + [XMM3]
std::swap(emitOp1, emitOp2);
}
else if (!copiesUpperBits && (targetReg == op3NodeReg))
{
// op3 = (op1 * op2) + op3
// 231 form: XMM1 = (XMM2 * XMM3) + XMM1
std::swap(emitOp1, emitOp3);
ins = _231form;
}

// else, targetReg == op1NodeReg or targetReg == ?
// no extra work needed
}

genHWIntrinsic_R_R_R_RM(ins, attr, targetReg, emitOp1->GetRegNum(), emitOp2->GetRegNum(), emitOp3);
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