Skip to content

Expose various integer intrinsics for Avx512F, Avx512BW, and Avx512CD #85833

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 23 commits into from
May 10, 2023
Merged

Expose various integer intrinsics for Avx512F, Avx512BW, and Avx512CD #85833

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
23 commits
Select commit Hold shift + click to select a range
3652db3
Expose AlignRight32 and AlignRight64 on Avx512F
tannergooding May 3, 2023
b9c9690
Expose RotateLeft and RotateRight for Avx512F
tannergooding May 3, 2023
f9158a8
Expose SumAbsoluteDifferencesInBlock32 for Avx512BW + DetectConflicts…
tannergooding May 4, 2023
2487a19
Exponse TernaryLogic for Avx512F
tannergooding May 5, 2023
6e72be6
Apply formatting patch
tannergooding May 5, 2023
6046e65
Merge remote-tracking branch 'dotnet/main' into avx512-5
tannergooding May 5, 2023
ea83d7b
Ensure side effects are preserved when optimizing certain intrinsic i…
tannergooding May 5, 2023
e58abbb
Ensure the instruction code has the SIMD prefix before trying to enco…
tannergooding May 5, 2023
a5323e2
Ensure side effects have been accounted for before swapping operands
tannergooding May 5, 2023
2584e7d
Move the complex ternary logic simplification logic to import, since …
tannergooding May 8, 2023
6636fba
Ensure gtNewSimdUnOpNode(GT_NOT) uses an in range constant for Ternar…
tannergooding May 8, 2023
acdfb9b
Remove a new assert added to AND_NOT, logging an issue instead
tannergooding May 8, 2023
49646ce
Add a missing `break;` statement
tannergooding May 9, 2023
1420642
Ensure val1/2/3 are GenTree** so swapping works and add a comment exp…
tannergooding May 9, 2023
1af17d8
Fix formatting of a comment
tannergooding May 9, 2023
f2d8378
Don't double encode the 'vvvv' bits for `emitOutputAM`
tannergooding May 9, 2023
bc081b6
Merge remote-tracking branch 'dotnet/main' into avx512-5
tannergooding May 9, 2023
94b5e53
Avoid an assert in gtNewSimdCreateBroadcastNode for TYP_LONG on 32-bit
tannergooding May 9, 2023
5d0a740
Ensure we use CHECK_SPILL_ALL
tannergooding May 9, 2023
d07bc37
Ensure mustExpand is handled for `RotateLeft(Vector###<long>)` on 32-bit
tannergooding May 10, 2023
afccab8
Make sure all tests are actually running and handle the "maybe no jmp…
tannergooding May 10, 2023
10c74fc
Handle a couple test issues and ensure we set the constant when norm…
tannergooding May 10, 2023
e751e9c
Ensure ValidateRemaining uses firstOp[i]
tannergooding May 10, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
10 changes: 10 additions & 0 deletions src/coreclr/jit/compiler.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2740,6 +2740,16 @@ class Compiler
GenTree* gtNewSimdSumNode(
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize);

#if defined(TARGET_XARCH)
GenTree* gtNewSimdTernaryLogicNode(var_types type,
GenTree* op1,
GenTree* op2,
GenTree* op3,
GenTree* op4,
CorInfoType simdBaseJitType,
unsigned simdSize);
#endif // TARGET_XARCH

GenTree* gtNewSimdUnOpNode(genTreeOps op,
var_types type,
GenTree* op1,
Expand Down
Loading