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@JongHeonChoi JongHeonChoi commented Nov 9, 2023

Initial patch of interpreter for RISCV64 at HelloWorld level.

cc @wscho77 @HJLeee @clamp03 @JongHeonChoi @t-mustafin @gbalykov @viewizard @ashaurtaev @sirntar @yurai007 @Bajtazar @tomeksowi

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clamp03 commented Nov 10, 2023

@jkotas We have updated CoreCLR interpreter for RISC-V because I think the interpreter is useful for debugging in our product issue where JITC on RISC-V does not work well. However, I find it has many problems. Cannot compile on x64 and arm64 (before this PR). Cannot run helloworld from the beginning on arm64/x64/riscv64. (It can only run the helloworld main function). So I just wonder, do you have a plan to complete the interpreter? Or will you keep the interpreter as it is now?

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jkotas commented Nov 10, 2023

We do not have any plans with the CoreCLR interpreter. We know that it is pretty broken.

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clamp03 commented Nov 10, 2023

Thank you for the comment. Okay. we need to use it very carefully.
Could you review this PR?

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We have updated CoreCLR interpreter for RISC-V because I think the interpreter is useful for debugging in our product issue where JITC on RISC-V does not work well

Could you enumerate the painspots with JITC? Perhaps it could be a starting point for a to-do list of improvements.

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clamp03 commented Nov 10, 2023

We fixed many bugs in coreclr and corefx unit tests on QEMU and Sifive2 devices.
Next year, we need to start testing, debugging and optimising tizenfx tests and big real applications on tizen riscv devices, which are very unstable environment in both hardware and software. Maybe all crashes and errors would be assigned to us because all crashes and errors occur when tests or applications are running. And as you know, fixing bugs in generated machine codes by JITC is very hard. I am so afraid of this situation. 😢 IMO we need to prepare tools (like createdump, debugging tools and logging tools), tizen risc-v CI and so on. Fixing the CoreCLR interpreter is one of them.

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