Skip to content

Conversation

@snickolls-arm
Copy link
Contributor

Adds encodings for bfcvtnt, fcvtlt, fcvtnt and fcvtxnt.

bfcvtnt z3.h, p0/m, z4.s
fcvtlt z0.d, p7/m, z1.s
fcvtlt z14.s, p7/m, z20.h
fcvtnt z18.h, p3/m, z9.s
fcvtnt z12.s, p3/m, z5.d
fcvtxnt z1.s, p2/m, z3.d

Contributing towards #94549.

@ghost ghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Feb 13, 2024
@ghost
Copy link

ghost commented Feb 13, 2024

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

Issue Details

Adds encodings for bfcvtnt, fcvtlt, fcvtnt and fcvtxnt.

bfcvtnt z3.h, p0/m, z4.s
fcvtlt z0.d, p7/m, z1.s
fcvtlt z14.s, p7/m, z20.h
fcvtnt z18.h, p3/m, z9.s
fcvtnt z12.s, p3/m, z5.d
fcvtxnt z1.s, p2/m, z3.d

Contributing towards #94549.

Author: snickolls-arm
Assignees: -
Labels:

area-CodeGen-coreclr

Milestone: -

@ryujit-bot
Copy link

Diff results for #98352

Throughput diffs

Throughput diffs for linux/arm64 ran on linux/x64

MinOpts (-0.01% to +0.00%)
Collection PDIFF
libraries.pmi.linux.arm64.checked.mch -0.01%
realworld.run.linux.arm64.checked.mch -0.01%

Details here


@kunalspathak kunalspathak changed the title Add ARM64 encodings for group IF_SVE_GQ_2A Add ARM64 encodings for group IF_SVE_GQ_3A Feb 13, 2024

// Expands an option that has different size operands (INS_OPTS_*_TO_*) into a pair of scalable options where
// the first describes the size of the destination operand and the second describes the size of the source operand.
std::pair<insOpts, insOpts> optExpandConversionPair(insOpts opt);
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

we do not use standard libraries function like std::pair. Can you instead change it to something like

Suggested change
std::pair<insOpts, insOpts> optExpandConversionPair(insOpts opt);
void optExpandConversionPair(insOpts opt, insOpts& dst, insOpts& src);

case INS_sve_fcvtnt:
if (id->idInsOpt() == INS_OPTS_S_TO_H)
{
code ^= (1 << 22 | 1 << 17);
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

can you instead change the below to:

// FCVTNT <Zd>.S, <Pg>/M, <Zn>.D SVE_GQ_3A 0110010011001010 101gggnnnnnddddd 64CA A000

- INST2(fcvtnt,            "fcvtnt",                0,                       IF_SVE_2BJ,              0x64CAA000,      0x650A3C00                  )
-   // FCVTNT  <Zd>.S, <Pg>/M, <Zn>.D                                                    SVE_GQ_3A           0110010011001010 101gggnnnnnddddd     64CA A000
+ INST2(fcvtnt,            "fcvtnt",                0,                       IF_SVE_2BJ,              0x6488A000,      0x650A3C00                  )
+    // FCVTNT  <Zd>.H, <Pg>/M, <Zn>.S                                                    SVE_GQ_3A           0110010010001000 101gggnnnnnddddd     6488 A000   

and then use |:

Suggested change
code ^= (1 << 22 | 1 << 17);
code |= (1 << 22 | 1 << 17);

case INS_sve_fcvtlt:
if (id->idInsOpt() == INS_OPTS_H_TO_S)
{
code ^= (1 << 22 | 1 << 17);
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

likewise for fcvtlt?

case INS_sve_fcvtxnt:
case INS_sve_bfcvtnt:
assert(isVectorRegister(reg1)); // ddddd
assert(isPredicateRegister(reg2)); // ggg
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Suggested change
assert(isPredicateRegister(reg2)); // ggg
assert(isLowPredicateRegister(reg2)); // ggg

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

and at other places too, the assert should be for LowPredicateRegister().

@snickolls-arm
Copy link
Contributor Author

@a74nh @kunalspathak @dotnet/arm64-contrib

Copy link
Contributor

@kunalspathak kunalspathak left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM. Thanks!

@kunalspathak
Copy link
Contributor

Failures are known and superpmi-x64 is clean.

@kunalspathak kunalspathak merged commit 9561bed into dotnet:main Feb 14, 2024
@ryujit-bot
Copy link

Diff results for #98352

Throughput diffs

Throughput diffs for linux/arm64 ran on windows/x64

MinOpts (-0.01% to +0.00%)
Collection PDIFF
realworld.run.linux.arm64.checked.mch -0.01%

Throughput diffs for osx/arm64 ran on windows/x64

MinOpts (-0.01% to +0.00%)
Collection PDIFF
realworld.run.osx.arm64.checked.mch -0.01%

Throughput diffs for windows/arm64 ran on windows/x64

MinOpts (-0.00% to +0.01%)
Collection PDIFF
libraries.pmi.windows.arm64.checked.mch +0.01%

Details here


Sign up for free to subscribe to this conversation on GitHub. Already have an account? Sign in.

Labels

area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI arm-sve Work related to arm64 SVE/SVE2 support

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants