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[RISC-V] Fix alignment for vector types #99589

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Merged
merged 6 commits into from
Mar 15, 2024
Merged

[RISC-V] Fix alignment for vector types #99589

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eacb0d2
[RISC-V] Fix alignment for vector types
clamp03 Mar 12, 2024
932adbd
[RISC-V] Fix typo
clamp03 Mar 12, 2024
af9281e
[RISC-V] Update comments
clamp03 Mar 14, 2024
a5a7a96
[RISC-V] Update Alignment
clamp03 Mar 14, 2024
e17ccd2
[RISC-V] Update comment
clamp03 Mar 14, 2024
d7e502e
[RISC-V] Update the comment
clamp03 Mar 14, 2024
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18 changes: 16 additions & 2 deletions src/coreclr/tools/Common/Compiler/VectorFieldLayoutAlgorithm.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -52,12 +52,19 @@ public override ComputedInstanceFieldLayout ComputeInstanceLayout(DefType defTyp
// to the same alignment as __m128, which is supported by the ABI.
alignment = new LayoutInt(8);
}
else if (defType.Context.Target.Architecture == TargetArchitecture.ARM64 || defType.Context.Target.Architecture == TargetArchitecture.RiscV64)
else if (defType.Context.Target.Architecture == TargetArchitecture.ARM64)
{
// The Procedure Call Standard for ARM 64-bit (with SVE support) defaults to
// 16-byte alignment for __m256.
alignment = new LayoutInt(16);
}
else if (defType.Context.Target.Architecture == TargetArchitecture.RiscV64)
{
// TODO-RISCV64: Update alignment to proper value when we implement RISC-V intrinsic.
// RISC-V Vector Extenstion Intrinsic Document
// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/vector_type_infos.adoc
alignment = new LayoutInt(16);
}
else
{
alignment = new LayoutInt(32);
Expand All @@ -73,12 +80,19 @@ public override ComputedInstanceFieldLayout ComputeInstanceLayout(DefType defTyp
// to the same alignment as __m128, which is supported by the ABI.
alignment = new LayoutInt(8);
}
else if (defType.Context.Target.Architecture == TargetArchitecture.ARM64 || defType.Context.Target.Architecture == TargetArchitecture.RiscV64)
else if (defType.Context.Target.Architecture == TargetArchitecture.ARM64)
{
// The Procedure Call Standard for ARM 64-bit (with SVE support) defaults to
// 16-byte alignment for __m256.
alignment = new LayoutInt(16);
}
else if (defType.Context.Target.Architecture == TargetArchitecture.RiscV64)
{
// TODO-RISCV64: Update alignment to proper value when we implement RISC-V intrinsic.
// RISC-V Vector Extenstion Intrinsic Document
// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/vector_type_infos.adoc
alignment = new LayoutInt(16);
}
else
{
alignment = new LayoutInt(64);
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11 changes: 11 additions & 0 deletions src/coreclr/vm/methodtablebuilder.cpp
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Expand Up @@ -10051,6 +10051,11 @@ void MethodTableBuilder::CheckForSystemTypes()
// The Procedure Call Standard for ARM 64-bit (with SVE support) defaults to
// 16-byte alignment for __m256.

pLayout->m_ManagedLargestAlignmentRequirementOfAllMembers = 16;
#elif defined(TARGET_RISCV64)
// TODO-RISCV64: Update alignment to proper value when we implement RISC-V intrinsic.
// RISC-V Vector Extenstion Intrinsic Document
// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/vector_type_infos.adoc
pLayout->m_ManagedLargestAlignmentRequirementOfAllMembers = 16;
#else
pLayout->m_ManagedLargestAlignmentRequirementOfAllMembers = 32; // sizeof(__m256)
Expand All @@ -10068,6 +10073,12 @@ void MethodTableBuilder::CheckForSystemTypes()
// 16-byte alignment for __m256.

pLayout->m_ManagedLargestAlignmentRequirementOfAllMembers = 16;

#elif defined(TARGET_RISCV64)
// TODO-RISCV64: Update alignment to proper value when we implement RISC-V intrinsic.
// RISC-V Vector Extenstion Intrinsic Document
// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/vector_type_infos.adoc
pLayout->m_ManagedLargestAlignmentRequirementOfAllMembers = 16;
#else
pLayout->m_ManagedLargestAlignmentRequirementOfAllMembers = 64; // sizeof(__m512)
#endif // TARGET_ARM elif TARGET_ARM64
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3 changes: 3 additions & 0 deletions src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Vector256.cs
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Expand Up @@ -36,6 +36,9 @@ public static unsafe class Vector256
internal const int Alignment = 8;
#elif TARGET_ARM64
internal const int Alignment = 16;
#elif TARGET_RISCV64
// TODO-RISCV64: Update alignment to proper value when we implement RISC-V intrinsic.
internal const int Alignment = 16;
#else
internal const int Alignment = 32;
#endif
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3 changes: 3 additions & 0 deletions src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Vector512.cs
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Expand Up @@ -36,6 +36,9 @@ public static unsafe class Vector512
internal const int Alignment = 8;
#elif TARGET_ARM64
internal const int Alignment = 16;
#elif TARGET_RISCV64
// TODO-RISCV64: Update alignment to proper value when we implement RISC-V intrinsic.
internal const int Alignment = 16;
#else
internal const int Alignment = 64;
#endif
Expand Down