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Jan 23, 2024
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ESP32-P4: Initial GPIO support #1109

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18c77a3
ESP32-P4: Initial GPIO support
bjoernQ Jan 23, 2024
803330b
CHANGELOG.md entry
bjoernQ Jan 23, 2024
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -13,6 +13,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0

- Add initial support for the ESP32-P4 (#1101)
- Implement `embedded_hal::pwm::SetDutyCycle` trait for `ledc::channel::Channel` (#1097)
- ESP32-P4: Add initial GPIO support (#1109)

### Fixed

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2 changes: 1 addition & 1 deletion esp-hal-common/Cargo.toml
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Expand Up @@ -66,7 +66,7 @@ esp32c2 = { version = "0.17.0", features = ["critical-section"], optional = true
esp32c3 = { version = "0.20.0", features = ["critical-section"], optional = true }
esp32c6 = { version = "0.11.0", features = ["critical-section"], optional = true }
esp32h2 = { version = "0.7.0", features = ["critical-section"], optional = true }
esp32p4 = { git = "https://github.com/esp-rs/esp-pacs", rev = "4c0dfd5", optional = true }
esp32p4 = { git = "https://github.com/esp-rs/esp-pacs", rev = "c801d10", optional = true }
esp32s2 = { version = "0.19.0", features = ["critical-section"], optional = true }
esp32s3 = { version = "0.23.0", features = ["critical-section"], optional = true }

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4 changes: 2 additions & 2 deletions esp-hal-common/devices/esp32p4/device.toml
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Expand Up @@ -17,7 +17,7 @@ peripherals = [
# "ecdsa",
# "efuse",
# "gpio_sd",
# "gpio",
"gpio",
# "h264_dma",
# "h264",
# "hmac",
Expand All @@ -33,7 +33,7 @@ peripherals = [
# "i3c_slv",
"interrupt_core0",
"interrupt_core1",
# "io_mux",
"io_mux",
# "isp",
# "jpeg",
# "lcd_cam",
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45 changes: 38 additions & 7 deletions esp-hal-common/src/gpio.rs
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Expand Up @@ -24,11 +24,13 @@

use core::{convert::Infallible, marker::PhantomData};

#[cfg(any(adc, dac))]
pub(crate) use crate::analog;
pub(crate) use crate::gpio;
use crate::peripherals::{GPIO, IO_MUX};
#[cfg(any(xtensa, esp32c3))]
pub(crate) use crate::rtc_pins;
pub use crate::soc::gpio::*;
pub(crate) use crate::{analog, gpio};

/// Convenience type-alias for a no-pin / don't care - pin
pub type NoPinType = Gpio0<Unknown>;
Expand Down Expand Up @@ -462,7 +464,7 @@ impl BankGpioRegisterAccess for Bank1GpioRegisterAccess {

pub fn connect_low_to_peripheral(signal: InputSignal) {
unsafe { &*GPIO::PTR }
.func_in_sel_cfg(signal as usize)
.func_in_sel_cfg(signal as usize - FUNC_IN_SEL_OFFSET)
.modify(|_, w| unsafe {
w.sel()
.set_bit()
Expand All @@ -475,7 +477,7 @@ pub fn connect_low_to_peripheral(signal: InputSignal) {

pub fn connect_high_to_peripheral(signal: InputSignal) {
unsafe { &*GPIO::PTR }
.func_in_sel_cfg(signal as usize)
.func_in_sel_cfg(signal as usize - FUNC_IN_SEL_OFFSET)
.modify(|_, w| unsafe {
w.sel()
.set_bit()
Expand Down Expand Up @@ -746,7 +748,7 @@ where
self.set_alternate_function(af);
if (signal as usize) <= INPUT_SIGNAL_MAX as usize {
unsafe { &*GPIO::PTR }
.func_in_sel_cfg(signal as usize)
.func_in_sel_cfg(signal as usize - FUNC_IN_SEL_OFFSET)
.modify(|_, w| unsafe {
w.sel()
.set_bit()
Expand All @@ -763,7 +765,7 @@ where
self.set_alternate_function(GPIO_FUNCTION);

unsafe { &*GPIO::PTR }
.func_in_sel_cfg(signal as usize)
.func_in_sel_cfg(signal as usize - FUNC_IN_SEL_OFFSET)
.modify(|_, w| w.sel().clear_bit());
self
}
Expand Down Expand Up @@ -800,6 +802,8 @@ where
_ => {}
}
}

#[cfg(not(any(esp32p4)))]
unsafe {
(&*GPIO::PTR).pin(GPIONUM as usize).modify(|_, w| {
w.int_ena()
Expand All @@ -810,6 +814,20 @@ where
.bit(wake_up_from_light_sleep)
});
}

#[cfg(any(esp32p4))]
unsafe {
// there is no NMI_ENABLE but P4 could trigger 4 interrupts
// we'll only support GPIO_INT0 for now
(&*GPIO::PTR).pin(GPIONUM as usize).modify(|_, w| {
w.int_ena()
.bits(gpio_intr_enable(int_enable, nmi_enable))
.int_type()
.bits(event as u8)
.wakeup_enable()
.bit(wake_up_from_light_sleep)
});
}
}

fn is_listening(&self) -> bool {
Expand Down Expand Up @@ -1035,6 +1053,7 @@ where
}
}

#[cfg(any(adc, dac))]
impl<const GPIONUM: u8> From<GpioPin<Unknown, GPIONUM>> for GpioPin<Analog, GPIONUM>
where
Self: GpioProperties,
Expand Down Expand Up @@ -1326,6 +1345,7 @@ where
}
}

#[cfg(any(adc, dac))]
impl<MODE, const GPIONUM: u8> GpioPin<MODE, GPIONUM>
where
Self: GpioProperties,
Expand Down Expand Up @@ -2714,11 +2734,22 @@ mod asynch {
});
}

#[cfg(not(any(esp32p4)))]
#[interrupt]
unsafe fn GPIO() {
handle_gpio_interrupt();
}

#[cfg(any(esp32p4))]
#[interrupt]
unsafe fn GPIO_INT0() {
handle_gpio_interrupt();
}

fn handle_gpio_interrupt() {
let intrs_bank0 = InterruptStatusRegisterAccessBank0::interrupt_status_read();

#[cfg(any(esp32, esp32s2, esp32s3))]
#[cfg(any(esp32, esp32s2, esp32s3, esp32p4))]
let intrs_bank1 = InterruptStatusRegisterAccessBank1::interrupt_status_read();

let mut intr_bits = intrs_bank0;
Expand All @@ -2732,7 +2763,7 @@ mod asynch {
// clear interrupt bits
Bank0GpioRegisterAccess::write_interrupt_status_clear(intrs_bank0);

#[cfg(any(esp32, esp32s2, esp32s3))]
#[cfg(any(esp32, esp32s2, esp32s3, esp32p4))]
{
let mut intr_bits = intrs_bank1;
while intr_bits != 0 {
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2 changes: 2 additions & 0 deletions esp-hal-common/src/soc/esp32/gpio.rs
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Expand Up @@ -60,6 +60,8 @@ use crate::{

pub const NUM_PINS: usize = 39;

pub(crate) const FUNC_IN_SEL_OFFSET: usize = 0;

pub type OutputSignalType = u16;
pub const OUTPUT_SIGNAL_MAX: u16 = 548;
pub const INPUT_SIGNAL_MAX: u16 = 539;
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2 changes: 2 additions & 0 deletions esp-hal-common/src/soc/esp32c2/gpio.rs
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Expand Up @@ -52,6 +52,8 @@ use crate::{

pub const NUM_PINS: usize = 20;

pub(crate) const FUNC_IN_SEL_OFFSET: usize = 0;

pub type OutputSignalType = u8;
pub const OUTPUT_SIGNAL_MAX: u8 = 128;
pub const INPUT_SIGNAL_MAX: u8 = 100;
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2 changes: 2 additions & 0 deletions esp-hal-common/src/soc/esp32c3/gpio.rs
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Expand Up @@ -53,6 +53,8 @@ use crate::{

pub const NUM_PINS: usize = 21;

pub(crate) const FUNC_IN_SEL_OFFSET: usize = 0;

pub type OutputSignalType = u8;
pub const OUTPUT_SIGNAL_MAX: u8 = 128;
pub const INPUT_SIGNAL_MAX: u8 = 100;
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2 changes: 2 additions & 0 deletions esp-hal-common/src/soc/esp32c6/gpio.rs
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Expand Up @@ -53,6 +53,8 @@ use crate::{

pub const NUM_PINS: usize = 30;

pub(crate) const FUNC_IN_SEL_OFFSET: usize = 0;

pub type OutputSignalType = u8;
pub const OUTPUT_SIGNAL_MAX: u8 = 128;
pub const INPUT_SIGNAL_MAX: u8 = 124;
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2 changes: 2 additions & 0 deletions esp-hal-common/src/soc/esp32h2/gpio.rs
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Expand Up @@ -54,6 +54,8 @@ use crate::{
// https://github.com/espressif/esp-idf/blob/df9310a/components/soc/esp32h2/gpio_periph.c#L42
pub const NUM_PINS: usize = 27;

pub(crate) const FUNC_IN_SEL_OFFSET: usize = 0;

pub type OutputSignalType = u8;
pub const OUTPUT_SIGNAL_MAX: u8 = 128;
pub const INPUT_SIGNAL_MAX: u8 = 124;
Expand Down
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