Skip to content

Fix FPGA-Level Simulation #24

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
merged 3 commits into from
Feb 6, 2020
Merged

Fix FPGA-Level Simulation #24

merged 3 commits into from
Feb 6, 2020

Conversation

davidbiancolin
Copy link
Contributor

FPGA-level simulation was busted mostly because I never added support for synthesizing the PLL that provides the GG-domain clock.

@davidbiancolin davidbiancolin requested a review from sagark February 6, 2020 02:10
sagark
sagark approved these changes Feb 6, 2020
View reviewed changes
Copy link
Member

@sagark sagark left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

lgtm

@davidbiancolin davidbiancolin merged commit f7915f6 into dev Feb 6, 2020
@davidbiancolin davidbiancolin deleted the fix-fl-sim branch February 6, 2020 02:14
@davidbiancolin davidbiancolin mentioned this pull request Feb 6, 2020
Merged
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

@sagark sagark sagark approved these changes

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

2 participants

@davidbiancolin @sagark