GitHub - jacobgualtieri/VHDL_Port_Map_Generator: This is a python script that automatically generates testbench templates for Verilog and VHDL source files. It parses the provided HDL source file for a module's name, parameters, and ports and then writes a testbench template for that module. This can be used to automate and streamline the process of setting up simulations for your HDL modules. I'd love to hear any feedback or constructive criticisms you may have (:

jacobgualtieri / VHDL_Port_Map_Generator Public

Notifications You must be signed in to change notification settings
Fork 0
Star 3

This is a python script that automatically generates testbench templates for Verilog and VHDL source files. It parses the provided HDL source file for a module's name, parameters, and ports and then writes a testbench template for that module. This can be used to automate and streamline the process of setting up simulations for your HDL modules.…

3 stars 0 forks Branches Tags Activity

Star

Notifications

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
.vscode		.vscode
README.txt		README.txt
andGate2_tb.v		andGate2_tb.v
andGate2_tb.vhd		andGate2_tb.vhd
orGate2_tb.v		orGate2_tb.v
orGate2_tb.vhd		orGate2_tb.vhd
testbenchWriter.py		testbenchWriter.py

Repository files navigation

Author: Jacob Gualtieri

~~ v1.1.0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Released: 7/3/2021

This script has been completely rewritten from the ground up!

This python3 script can read basic Verilog and VHDL files and automatically
create testbenches testbench templates for them.

The script has changed entirely. It is now much more organized and readable

As of this version, these are the limitations:
 - The script can only create Verilog testbenches from Verilog source files,
   and the same is true for VHDL.
 - There is no user input at this point, as all filenames and paths have been
   hardcoded.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~