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[AArch64] optimise SVE cvt intrinsics with no active lanes #104809

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Merged
merged 5 commits into from
Aug 29, 2024
Merged

[AArch64] optimise SVE cvt intrinsics with no active lanes #104809

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f77215a
[AArch64] optimise SVE cvt intrinsics with no active lanes
Lukacma Aug 19, 2024
82cc1e3
Fix function naming and tests and added test for all active lanes
Lukacma Aug 22, 2024
c6b530e
Fix comment and add poison value check
Lukacma Aug 27, 2024
e5340ce
add tests for poison/undef and fix intrinsics name
Lukacma Aug 28, 2024
1a67c34
Merge branch 'main' into sve_falseopt_cvt
Lukacma Aug 29, 2024
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63 changes: 62 additions & 1 deletion llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1073,6 +1073,33 @@ static bool isAllActivePredicate(Value *Pred) {
m_ConstantInt<AArch64SVEPredPattern::all>()));
}

// Simplify unary operation where predicate has all inactive lanes by replacing
// instruction with its operand
static std::optional<Instruction *>
instCombineSVENoActiveReplace(InstCombiner &IC, IntrinsicInst &II,
bool hasInactiveVector) {
int PredOperand = hasInactiveVector ? 1 : 0;
int ReplaceOperand = hasInactiveVector ? 0 : 1;
if (match(II.getOperand(PredOperand), m_ZeroInt())) {
IC.replaceInstUsesWith(II, II.getOperand(ReplaceOperand));
return IC.eraseInstFromFunction(II);
}
return std::nullopt;
}

// Simplify unary operation where predicate has all inactive lanes or
// replace unused first operand with undef when all lanes are active
static std::optional<Instruction *>
instCombineSVEAllOrNoActiveUnary(InstCombiner &IC, IntrinsicInst &II) {
if (isAllActivePredicate(II.getOperand(1)) &&
!isa<llvm::UndefValue>(II.getOperand(0)) &&
!isa<llvm::PoisonValue>(II.getOperand(0))) {
Value *Undef = llvm::UndefValue::get(II.getType());
return IC.replaceOperand(II, 0, Undef);
}
return instCombineSVENoActiveReplace(IC, II, true);
}

// Erase unary operation where predicate has all inactive lanes
static std::optional<Instruction *>
instCombineSVENoActiveUnaryErase(InstCombiner &IC, IntrinsicInst &II,
Expand Down Expand Up @@ -2109,7 +2136,41 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
switch (IID) {
default:
break;

case Intrinsic::aarch64_sve_fcvt_bf16f32:
case Intrinsic::aarch64_sve_fcvt_f16f32:
case Intrinsic::aarch64_sve_fcvt_f16f64:
case Intrinsic::aarch64_sve_fcvt_f32f16:
case Intrinsic::aarch64_sve_fcvt_f32f64:
case Intrinsic::aarch64_sve_fcvt_f64f16:
case Intrinsic::aarch64_sve_fcvt_f64f32:
case Intrinsic::aarch64_sve_fcvtlt_f32f16:
case Intrinsic::aarch64_sve_fcvtlt_f64f32:
case Intrinsic::aarch64_sve_fcvtnt_bf16f32:
case Intrinsic::aarch64_sve_fcvtnt_f16f32:
case Intrinsic::aarch64_sve_fcvtnt_f32f64:
case Intrinsic::aarch64_sve_fcvtx_f32f64:
case Intrinsic::aarch64_sve_fcvtxnt_f32f64:
case Intrinsic::aarch64_sve_fcvtzs:
case Intrinsic::aarch64_sve_fcvtzs_i32f16:
case Intrinsic::aarch64_sve_fcvtzs_i32f64:
case Intrinsic::aarch64_sve_fcvtzs_i64f16:
case Intrinsic::aarch64_sve_fcvtzs_i64f32:
case Intrinsic::aarch64_sve_fcvtzu:
case Intrinsic::aarch64_sve_fcvtzu_i32f16:
case Intrinsic::aarch64_sve_fcvtzu_i32f64:
case Intrinsic::aarch64_sve_fcvtzu_i64f16:
case Intrinsic::aarch64_sve_fcvtzu_i64f32:
case Intrinsic::aarch64_sve_scvtf:
case Intrinsic::aarch64_sve_scvtf_f16i32:
case Intrinsic::aarch64_sve_scvtf_f16i64:
case Intrinsic::aarch64_sve_scvtf_f32i64:
case Intrinsic::aarch64_sve_scvtf_f64i32:
case Intrinsic::aarch64_sve_ucvtf:
case Intrinsic::aarch64_sve_ucvtf_f16i32:
case Intrinsic::aarch64_sve_ucvtf_f16i64:
case Intrinsic::aarch64_sve_ucvtf_f32i64:
case Intrinsic::aarch64_sve_ucvtf_f64i32:
return instCombineSVEAllOrNoActiveUnary(IC, II);
case Intrinsic::aarch64_sve_st1_scatter:
case Intrinsic::aarch64_sve_st1_scatter_scalar_offset:
case Intrinsic::aarch64_sve_st1_scatter_sxtw:
Expand Down
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