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[DAG] Remove OneUse restriction on sext when folding (shl (sext (add_nsw x, c1)), c2) #68972

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[DAG] Remove OneUse restriction on sext when folding (shl (sext (add_nsw x, c1)), c2) #68972

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3 changes: 1 addition & 2 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10054,8 +10054,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
// TODO: Should we limit this with isLegalAddImmediate?
if (N0.getOpcode() == ISD::SIGN_EXTEND &&
N0.getOperand(0).getOpcode() == ISD::ADD &&
N0.getOperand(0)->getFlags().hasNoSignedWrap() && N0->hasOneUse() &&
N0.getOperand(0)->hasOneUse() &&
N0.getOperand(0)->getFlags().hasNoSignedWrap() &&
TLI.isDesirableToCommuteWithShift(N, Level)) {
SDValue Add = N0.getOperand(0);
SDLoc DL(N0);
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11 changes: 11 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Expand Up @@ -3370,6 +3370,17 @@ X86TargetLowering::preferredShiftLegalizationStrategy(
ExpansionFactor);
}

bool X86TargetLowering::isDesirableToCommuteWithShift(
const SDNode *N, CombineLevel Level) const {
assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
N->getOpcode() == ISD::SRL) &&
"Expected shift op");
SDValue N0 = N->getOperand(0).getOpcode() == ISD::SIGN_EXTEND
? N->getOperand(0)->getOperand(0)
: N->getOperand(0);
return N0.hasOneUse();
}

bool X86TargetLowering::shouldSplatInsEltVarIndex(EVT VT) const {
// Any legal vector type can be splatted more efficiently than
// loading/spilling from memory.
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3 changes: 3 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.h
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Expand Up @@ -1172,6 +1172,9 @@ namespace llvm {
preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
unsigned ExpansionFactor) const override;

bool isDesirableToCommuteWithShift(const SDNode *N,
CombineLevel Level) const override;

bool shouldSplatInsEltVarIndex(EVT VT) const override;

bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override {
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18 changes: 7 additions & 11 deletions llvm/test/CodeGen/RISCV/riscv-shifted-extend.ll
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Expand Up @@ -5,12 +5,10 @@
define void @test(ptr nocapture noundef writeonly %array1, i32 noundef signext %a, i32 noundef signext %b) {
; RV64-LABEL: test:
; RV64: # %bb.0: # %entry
; RV64-NEXT: addiw a3, a1, 5
; RV64-NEXT: slli a4, a3, 2
; RV64-NEXT: add a4, a0, a4
; RV64-NEXT: sw a2, 0(a4)
; RV64-NEXT: addi a3, a1, 5
; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: sw a2, 20(a0)
; RV64-NEXT: sw a2, 24(a0)
; RV64-NEXT: sw a3, 140(a0)
; RV64-NEXT: ret
Expand All @@ -34,18 +32,16 @@ entry:
define void @test1(ptr nocapture noundef %array1, i32 noundef signext %a, i32 noundef signext %b, i32 noundef signext %x) {
; RV64-LABEL: test1:
; RV64: # %bb.0: # %entry
; RV64-NEXT: addiw a4, a1, 5
; RV64-NEXT: slli a5, a4, 2
; RV64-NEXT: add a5, a0, a5
; RV64-NEXT: mv a6, a4
; RV64-NEXT: addi a4, a1, 5
; RV64-NEXT: mv a5, a4
; RV64-NEXT: bgtz a3, .LBB1_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a6, a2
; RV64-NEXT: mv a5, a2
; RV64-NEXT: .LBB1_2: # %entry
; RV64-NEXT: sw a6, 0(a5)
; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: sw a6, 24(a0)
; RV64-NEXT: sw a5, 20(a0)
; RV64-NEXT: sw a5, 24(a0)
; RV64-NEXT: sw a4, 140(a0)
; RV64-NEXT: ret
entry:
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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/X86/pr65895.ll
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Expand Up @@ -21,10 +21,11 @@ define i32 @PR65895() {
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: jmp .LBB0_2
; CHECK-NEXT: .LBB0_3: # %for.end
; CHECK-NEXT: movzbl %al, %ecx
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To address this can you add the OneUse checks back to the x86 version of isDesirableToCommuteWithShift?

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done

; CHECK-NEXT: addb $-3, %al
; CHECK-NEXT: movsbl %al, %eax
; CHECK-NEXT: movl %eax, d(%rip)
; CHECK-NEXT: leal 247(%rax,%rax,2), %eax
; CHECK-NEXT: leal 241(%rax,%rcx,2), %eax
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This is an objective regression.

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fixed

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Regression still needs fixing

; CHECK-NEXT: movb $1, c(%rip)
; CHECK-NEXT: movsbq %al, %rax
; CHECK-NEXT: movq %rax, e(%rip)
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