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[NFC] Use references to avoid copying #99863

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Merged
merged 14 commits into from
Aug 9, 2024
Merged

[NFC] Use references to avoid copying #99863

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b15c063
Modified auto to auto& for MachineOperand objects
pratyay-p Jul 22, 2024
8ab5481
Merge branch 'llvm:main' into main
pratyay-p Jul 26, 2024
d559666
Merge branch 'main' into main
pratyay-p Aug 2, 2024
a2c1ada
Fixed formatting in RegAllocFast.cpp
pratyay-p Aug 2, 2024
6f20f88
Fixed formatting in WindowScheduler.cpp
pratyay-p Aug 2, 2024
a44f623
Merge branch 'llvm:main' into main
pratyay-p Aug 6, 2024
995536d
Add const to MISpilledOperands
pratyay-p Aug 6, 2024
051288b
Fix clang-format issues
pratyay-p Aug 6, 2024
260652b
Merge branch 'main' into main
pratyay-p Aug 7, 2024
b38ea33
Merge branch 'llvm:main' into main
pratyay-p Aug 7, 2024
eb25e8a
Merge branch 'llvm:main' into main
pratyay-p Aug 9, 2024
24019a6
Don't use ref. since NewMI is modified
pratyay-p Aug 9, 2024
d5587a1
Merge remote-tracking branch 'refs/remotes/origin/main'
pratyay-p Aug 9, 2024
7164036
Copy instead of using reference
pratyay-p Aug 9, 2024
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/RegAllocFast.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -584,7 +584,7 @@ void RegAllocFastImpl::spill(MachineBasicBlock::iterator Before,
SpilledOperandsMap;
for (MachineOperand *MO : LRIDbgOperands)
SpilledOperandsMap[MO->getParent()].push_back(MO);
for (auto MISpilledOperands : SpilledOperandsMap) {
for (auto &MISpilledOperands : SpilledOperandsMap) {
MachineInstr &DBG = *MISpilledOperands.first;
// We don't have enough support for tracking operands of DBG_VALUE_LISTs.
if (DBG.isDebugValueList())
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/WindowScheduler.cpp
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Expand Up @@ -318,7 +318,7 @@ void WindowScheduler::generateTripleMBB() {
auto *NewMI = MF->CloneMachineInstr(MI);
DenseMap<Register, Register> NewDefs;
// New defines are updated.
for (auto MO : NewMI->all_defs())
for (const auto &MO : NewMI->all_defs())
if (MO.isReg() && MO.getReg().isVirtual()) {
Register NewDef =
MRI->createVirtualRegister(MRI->getRegClass(MO.getReg()));
Expand Down Expand Up @@ -699,7 +699,7 @@ unsigned WindowScheduler::getOriStage(MachineInstr *OriMI, unsigned Offset) {
Register WindowScheduler::getAntiRegister(MachineInstr *Phi) {
assert(Phi->isPHI() && "Expecting PHI!");
Register AntiReg;
for (auto MO : Phi->uses()) {
for (const auto &MO : Phi->uses()) {
if (MO.isReg())
AntiReg = MO.getReg();
else if (MO.isMBB() && MO.getMBB() == MBB)
Expand Down