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VSDBabySoC
VSDBabySoC PublicVSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
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MYTH-workshop
MYTH-workshop PublicA 5-day workshop to implement a RISC-V based processor named MYTH from both SW and HW aspects.
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PASC
PASC PublicForked from jbush001/PASC
Parallel Array of Simple Cores. Multicore processor.
Verilog 1
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GeneticOptimizer
GeneticOptimizer PublicA DNN built from scratch, featuring multiple fully-connected layers and utilizing the Genetic Algorithm as the optimizer.
Python 1
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jbush001/PASC
jbush001/PASC PublicParallel Array of Simple Cores. Multicore processor.
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