This project demonstrates end-to-end ASIC design and functional verification of a lightweight Machine Learning (ML) accelerator integrated into a custom System-on-Chip (SoC). The entire verification flow is implemented using SystemVerilog, UVM (Universal Verification Methodology), and Python scripting for automation.
- β Design a simplified ML accelerator (Matrix Multiply Unit)
- β Integrate it into a RISC-V-based SoC (optional extension)
- β Develop a functional SystemVerilog testbench
- β Build a UVM-based verification environment
- β Use Python for test automation and results validation
- β Emulate the real-world design/verification process for Amazon ASICs
asic-soc-ml-accelerator-verification/
βββ rtl/ # RTL designs (SystemVerilog)
β βββ mma.v # Matrix Multiply Accelerator
βββ tb/ # Testbenches
β βββ mma_tb.sv # Functional testbench
βββ scripts/ # Automation scripts
β βββ run_verilator.py # Python-based test automation
βββ README.md # Project overview and setup
βββ Makefile # Simulation automation
βββ .gitignore
- SystemVerilog β RTL & testbench
- UVM β Reusable verification environment (coming next)
- Python β Test automation and data validation
- Verilator β Open-source simulation
- RISC-V Core (optional) β Integration with open-source CPU
-
Install Verilator:
sudo apt update sudo apt install -y verilator
-
Run Python Test Generator:
python3 scripts/run_verilator.py
-
Simulate using Makefile (WIP):
make
Detailed simulation and verification instructions will be added with the testbench and UVM flow.
This project is part of a hardware-centric portfolio built specifically to match the ASIC Design Verification Engineer role at top Semiconductor Designing Companies of the world. It demonstrates my passion for:
- Hardware/software co-design
- ML accelerator design
- Functional verification using UVM
- Scripting and automation in hardware development
Rehan Mohammed Qureshi
π Dallas, Texas, USA
π§ [email protected]
π LinkedIn