RISC-V targets do not support ARM "thread mode" check

[Disasm]

async-on-embedded/async-embedded/src/executor.rs

Lines 203 to 207 in 47eb470

	fn in_thread_mode() -> bool {
	const SCB_ICSR: *const u32 = 0xE000_ED04 as *const u32;
	// NOTE(unsafe) single-instruction load with no side effects
	unsafe { SCB_ICSR.read_volatile() as u8 == 0 }
	}

This code checks for a value of the VECTACTIVE field (only for bits 7..0 of the 9-bit field). This value corresponds to the current interrupt number handled (0 for none).

I wonder what should we use here for RISC-V. @ilya-epifanov any ideas?