About

VLSI Mentoring Portal for the 2026 Silicon University Batch.

Resources

• LITERATURE
  • Clifford Cummings, State Machine Coding Styles for Synthesis, SNUG, 1998 (PDF)
  • Clifford Cummings, Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!, SNUG, 2000 (PDF)
  • Clifford Cummings, et.al., Asynchronous & Synchronous Reset Design Techniques - Part Deux, SNUG, 2003 (PDF)
  • Clifford Cummings Google Scholar A great resource of papers on practical digital design.
• ONLINE
  • Verilog Tutorials from ChipVerify: for begineers that take you from basic datatypes to building hardware circuits.

Projects

Digital Temperature Monitor

• Follow this template GitHub Repo

Sessions

Sessions by Mr. Sujit Panda

• 20 Mar 2025

  • Figure-1 Arbiter design problem.
    • Design an arbiter that takes in multiple requests and services them one by one in the priority order $r1 > r2 > r3$
    • Acknowledgement will be asserted for one cycle for a request. If the request remains high even after that, it will be considered a new request. If multiple requests are asserted at the same time, they will be services in order of priority.
    • Design a modification to the above problem for Round-Robin priority. At reset you start with the priority $r1 > r2 > r3$, if you service say $r1$ then move it to the end ie. $r2 > r3 > r1$ and so on.
    • Alongwith the code, please upload a testplan too. It may be in the form of a table (xls is good) with the following columns.
      • 1. Feature
        2. Description
        3. Testcase description
    • Lets say we identify 4 features to be tested...
    • 1. Reset
      2. Single req asserted
      3. Multiple req asserted
      4. Consecutive requests on the same line
    • In the description column mention in your words waht it means and what are the sub-scenarios you want to test in that.
    • In the testcase description column mention the sequence of operation you would want to do in a testcase.
    • Doing this will help you understand the fallacies of your design and will help you think of all scenarios while designing itself.
  • And all the three Cummings Papers are a must read.

• 27 Feb 2025

  • Figure-1 Positive-edge detector.
  • Figure-2 Counter.
  • The first one is a positive edge detector and the second one is a counter.
  • For the first one, the reset (rstn) is async, active low (the reset that i have drawn is wrong. It should be inverse of what is drawn). The input signal a is synchronous to the clk. Whenever a goes high, the output signal b should go high for 1 clock cycle. When reset is asserted, output b remains at 0.
  • For the second one, reset (rstn) is async active low. The counter (cntr) remains at 0 while under reset. When out of reset, it counts only if en signal is high, else it remains at 0. The counter upcounts if the signal up_down is high, else it downcounts. If the hold signal is high, the counter pauses at whatever count it is. It continues counting when hold is low.

• 15 Feb 2025

  • Figure-1 Combinarotiral problem.
  • Figure-2 Sequential problem.
  • Write one verilog module for each of these. Write a testbench for each. Drive some stimulus to check that it works as expected.
  • For the second one, the provided waveform is representative....to describe it, b and c are delayed versions of a. Signal b is delayed by one cycle and c is delayed by 2 cycles with respect to a. The circuit works on the positive edge of the clock. Outputs go to 0 when rstn=0. The reset (rstn) is an asynchronous, active low one. NOTE The reset is inverted mistakenly!

• 14 Feb 2025

  • Please go through these concepts in Verilog. Whatever modules code, we will need these to design and test them (Tutorials from ChipVerify are a good resource):
    • Ports (input/output/inout)
    • Variables (reg, wire)
    • always blocks:
      • combinatorial, sequential
      • blcoking, non-blocking
    • assign statements
    • initial block
    • timescale and delays
    • $display, $finish
    • Testbench:
      • instatiation of design
      • clock generation
      • driving stimulus
      • sampling outputs and checking

Student GitHub Pages

• Amit