This repository contains materials for the course: "Next-Generation Semiconductors: RISC-V, AI, and TL-Verilog", sponsored by Global Initiative of Academic Networks (GIAN).

Recorded Videos

• Day1-I (Mon 12/09/24)
• Day1-II
• Day2-I (Tue 12/10/24)
  • Lab2-Calc: Sequential Ckt, Zero-Delay Model, Fibonacci; Lab:Counter; Lab-Seq-Calc-Soln;
  • Intro2Pipeline-Pythagoras; Lab:Calc in Pipeline; Demo-Calc Start Pnt; Lab: Connecting Outputs;
• Day2-II
• Day3-I (Wed 12/11/24)
• Day3-II
• Day4-I (Thu 12/12/24)
• Day4-II
• Day5-I (Fri 12/13/24)
• Day5-II
• Day6-I (Mon 12/16/24)
• Day6-II

Course Materials

• Slides
• Nandgame
• Wokwi Starting Template for Tiny Tapeout
• Matt Venn's "Microchip Manufacturing - How computer chips get made!" Video
• Starting-point code for:
  • Calculator
  • Calculator in Module 4
  • CPU
  • Empty Template for Final Projects
  • Reference designs, other starter templates, and past projects
• Reference solutions (Ctrl-Click for new tab)
• Handouts
  • Instructions for Programming Your FPGA and Taping Out Your ASIC
  • RISC-V Decode Tables
  • Human CPU Cards

Communication

• Join TL-Verilog User's Slack Workspace and join #gian-course channel.
• Contact instructors:
  • Steve Hoover: LinkedIn, email
  • Dr. Srinivas Boppu: LinkedIn
  • Dr. Ayan Palchaudhuri

Credits

• Global Initiative of Academic Networks (GIAN) provided the grant to make the delivery of this course possible.
• Efabless: Provides the chipIgnite Shuttle program, which, in collaboration with Google and Skywater, provides low-cost silicon tapeouts.
• Tiny Tapeout: Enables an ultra-low-cost path to silicon leveraging the chipIgnite Shuttle program including the Wokwi-based design environment, build flows, and boards (designed by Psychogenic Technologies) that are used in this course.
• Redwood EDA: Provides course instruction, content, and the free Makerchip platform for open-source TL-Verilog-based design.
• Hundreds of open-source contributors responsible for the open-source EDA tools and flows utilized in this course.