Python script for generating lookup tables for the gm/ID design methodology and much more ...
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Updated
Apr 24, 2025 - Python
Python script for generating lookup tables for the gm/ID design methodology and much more ...
ASIC implementation flow infrastructure
An experimental package manager and development tool for Hardware Description Languages (HDL).
SimIO is a collection of virtualized components to interact with a (System)Verilog simulation.
USAGI is a Python script designed to automate the process of synthesizing and performing gate-level simulations for digital designs across a range of cycle times.
Generator for wokwi schematics that implement lookup tables in conjunctive normal form (CNF), i.e. with AND and OR gates
🖋 Typeset Quartus II waveform files using TikZ (LaTeX)
🖋 Typeset Quartus II schematics using TikZ (LaTeX)
Transpiles a subset of Python functions into synthesizable SystemVerilog.
A Python-based tool for generating Verilog modules with features including customizable state machines, port definitions, and state diagrams using Graphviz. Ideal for FPGA and ASIC design workflows.
🗃 Digital design / 3D model classifier
Finding computer vision algorithms that I can easily accelerate using a FPGA.
This project implements a Moore Machine in Python and a Moore Machine Graphical User Interface in Java. A Moore Machine is a finite state machine where the outputs depend only on the current state.
Digital Logic Course - Designing & Implementing a Processor
物性・回路・プロセス・設計・テストを貫く一貫教育体系。 基礎から応用・実践までの構造的理解を重視。An integrated educational framework covering semiconductor physics, circuit design, fabrication processes, and testing. Emphasizes structured understanding from fundamentals to advanced and practical applications.
parity calculator for the given bit stream
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