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1. opentitan opentitan Public

   Forked from lowRISC/opentitan

   OpenTitan: Open source silicon root of trust

   SystemVerilog

2. pyvsc pyvsc Public

   Forked from fvutils/pyvsc

   Python packages providing a library for Verification Stimulus and Coverage

   Python

3. style-guides style-guides Public

   Forked from lowRISC/style-guides

   lowRISC Style Guides

4. lowRISC/ibex lowRISC/ibex Public

   Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

   SystemVerilog 1.6k 638

5. chipsalliance/riscv-dv chipsalliance/riscv-dv Public

   Random instruction generator for RISC-V processor verification

   Python 1.1k 353