Initial support for microchip cec1702

boards/arm/secureiot1702/CMakeLists.txt

@@ -0,0 +1,2 @@
+zephyr_library()
+zephyr_library_sources(pinmux.c)

boards/arm/secureiot1702/Kconfig.board

@@ -0,0 +1,4 @@
+config BOARD_SECUREIOT1702
+	bool "Microchip SecureIoT1702"
+	depends on SOC_SERIES_CEC
+	select HAS_DTS

boards/arm/secureiot1702/Kconfig.defconfig

@@ -0,0 +1,6 @@
+if BOARD_SECUREIOT1702
+
+config BOARD
+	default "secureiot1702"
+
+endif

boards/arm/secureiot1702/doc/secureiot1702.rst

@@ -0,0 +1,73 @@
+.. _secureiot1702:
+
+Microchip SecureIoT1702
+#######################
+
+Overview
+********
+
+Board configuration for Microchip CEC1702 demo board. This is a cryptographic
+embedded controlled based on an ARM Cortex-M4.
+
+Highlights of the board:
+
+- CEC1702 32-bit ARM® Cortex®-M4F Controller with Integrated Crypto
+- Compact, high-contrast, serial graphic LCD Display Module with back-light
+- 2x4 matrix of push buttons inputs
+- USB-UART Converter as debug interface
+- Potentiometer to ADC channel
+- Serial Quad I/O (SQI) flash
+- OTP programmable in CEC1702
+- Two expansion headers compatible with MikroElektronika mikroBUS™ Expansion interface
+
+More information can be found from `SecureIoT1702 website`_ and
+`CEC1702 website`_. The SoC programming information is available
+in `CEC1702 datasheet`_.
+
+Supported Features
+==================
+
+Following devices are supported:
+
+- Nested Vectored Interrupt Controller (NVIC)
+- System Tick System Clock (SYSTICK)
+- Serial Ports (NS16550)
+- Quad Master-only SPI controller (QMSPI)
+
+
+Connections and IOs
+===================
+
+Please refer to the `SecureIoT1702 schematics`_ for the pin routings.
+Additional devices can be connected via mikroBUS expansion interface.
+
+Programming and Debugging
+*************************
+
+Flashing
+========
+[How to use this board with Zephyr and how to flash a Zephyr binary on this
+device]
+
+
+Debugging
+=========
+[ How to debug this board]
+
+
+References
+**********
+
+.. target-notes::
+
+.. _CEC1702 website:
+   http://www.microchip.com/CEC1702
+
+.. _CEC1702 datasheet:
+   http://www.microchip.com/p/207/
+
+.. _SecureIoT1702 website:
+   http://www.microchip.com/Developmenttools/ProductDetails.aspx?PartNO=DM990012
+
+.. _SecureIoT1702 schematics:
+   http://microchipdeveloper.com/secureiot1702:schematic

boards/arm/secureiot1702/dts_fixup.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2017 Crypta Labs Ltd
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is a temporary workaround for mapping of the generated information
+ * to the current driver definitions.  This will be removed when the drivers
+ * are modified to handle the generated information, or the mapping of
+ * generated data matches the driver definitions.
+ */
+
+#define DT_NUM_IRQ_PRIO_BITS			DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_NS16550_REG_SHIFT		DT_NS16550_400F2400_REG_SHIFT
+#define DT_UART_NS16550_PORT_0_BASE_ADDR	DT_NS16550_400F2400_BASE_ADDRESS
+#define DT_UART_NS16550_PORT_0_CLK_FREQ		DT_NS16550_400F2400_CLOCK_FREQUENCY
+#define CONFIG_UART_NS16550_PORT_0_NAME		DT_NS16550_400F2400_LABEL
+#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE	DT_NS16550_400F2400_CURRENT_SPEED
+
+#define DT_UART_NS16550_PORT_1_BASE_ADDR	DT_NS16550_400F2800_BASE_ADDRESS
+#define DT_UART_NS16550_PORT_1_CLK_FREQ		DT_NS16550_400F2800_CLOCK_FREQUENCY
+#define CONFIG_UART_NS16550_PORT_1_NAME		DT_NS16550_400F2800_LABEL
+#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE	DT_NS16550_400F2800_CURRENT_SPEED

boards/arm/secureiot1702/pinmux.c

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2017 Crypta Labs Ltd
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <init.h>
+#include <kernel.h>
+
+#include "soc.h"
+
+static int board_init(struct device *dev)
+{
+#ifdef CONFIG_UART_NS16550_PORT_0
+	/* Set clock request, muxing and power up UART0 */
+	PCR_INST->CLK_REQ_2_b.UART_0_CLK_REQ = 1;
+	GPIO_100_137_INST->GPIO_104_PIN_CONTROL_b.MUX_CONTROL = 1;
+	GPIO_100_137_INST->GPIO_105_PIN_CONTROL_b.MUX_CONTROL = 1;
+	UART0_INST->CONFIG = 0;
+	UART0_INST->ACTIVATE = 1;
+#endif
+#ifdef CONFIG_UART_NS16550_PORT_1
+	/* Set clock request, muxing, UART1_RX_EN and power up UART1 */
+	PCR_INST->CLK_REQ_2_b.UART_1_CLK_REQ = 1;
+	GPIO_140_176_INST->GPIO_170_PIN_CONTROL_b.MUX_CONTROL = 2;
+	GPIO_140_176_INST->GPIO_171_PIN_CONTROL_b.MUX_CONTROL = 2;
+	GPIO_100_137_INST->GPIO_113_PIN_CONTROL_b.GPIO_DIRECTION = 1;
+	UART1_INST->CONFIG = 0;
+	UART1_INST->ACTIVATE = 1;
+#endif
+#ifdef CONFIG_SPI_0
+	/* Set clock request, muxing and drive strength */
+	PCR_INST->CLK_REQ_4_b.QSPI_CLK_REQ = 1;
+	GPIO_040_076_INST->GPIO_055_PIN_CONTROL_b.MUX_CONTROL = 2;
+	GPIO_040_076_INST->GPIO_056_PIN_CONTROL_b.MUX_CONTROL = 2;
+	GPIO_200_236_INST->GPIO_223_PIN_CONTROL_b.MUX_CONTROL = 2;
+	GPIO_200_236_INST->GPIO_224_PIN_CONTROL_b.MUX_CONTROL = 2;
+	GPIO_200_236_INST->GPIO_227_PIN_CONTROL_b.MUX_CONTROL = 2;
+	GPIO_000_036_INST->GPIO_016_PIN_CONTROL_b.MUX_CONTROL = 2;
+	GPIO_PIN_CONTROL_2_INST->GPIO_055_PIN_CONTROL_2_b.DRIVE_STRENGTH = 2;
+	GPIO_PIN_CONTROL_2_INST->GPIO_056_PIN_CONTROL_2_b.DRIVE_STRENGTH = 2;
+	GPIO_PIN_CONTROL_2_INST->GPIO_223_PIN_CONTROL_2_b.DRIVE_STRENGTH = 2;
+	GPIO_PIN_CONTROL_2_INST->GPIO_224_PIN_CONTROL_2_b.DRIVE_STRENGTH = 2;
+	GPIO_PIN_CONTROL_2_INST->GPIO_227_PIN_CONTROL_2_b.DRIVE_STRENGTH = 2;
+	GPIO_PIN_CONTROL_2_INST->GPIO_016_PIN_CONTROL_2_b.DRIVE_STRENGTH = 2;
+#endif
+
+	return 0;
+}
+
+SYS_INIT(board_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

boards/arm/secureiot1702/secureiot1702.dts

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2017 Crypta Labs Ltd
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "microchip/cec1702.dtsi"
+
+/ {
+	model = "Microchip SecureIoT1702 board";
+	compatible = "microchip,secureiot1702", "microchip,cec1702";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,flash = &flash0;
+	};
+};
+
+&uart0 {
+	status = "ok";
+	current-speed = <115200>;
+};
+

boards/arm/secureiot1702/secureiot1702_defconfig

@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_SOC_SERIES_CEC=y
+CONFIG_SOC_CEC1702=y
+CONFIG_BOARD_SECUREIOT1702=y
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
+
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# No DT support for these yet
+CONFIG_UART_NS16550=y
+CONFIG_UART_NS16550_PORT_0=y
+CONFIG_UART_NS16550_PORT_1=y
+

drivers/serial/uart_ns16550.c

@@ -190,14 +190,22 @@
 
 #define IIRC(dev) (DEV_DATA(dev)->iir_cache)
 
+#ifdef CONFIG_NS16550_REG_SHIFT
+#define UART_REG_ADDR_INTERVAL (1<<CONFIG_NS16550_REG_SHIFT)
+#endif
+
 #ifdef UART_NS16550_ACCESS_IOPORT
 #define INBYTE(x) sys_in8(x)
 #define OUTBYTE(x, d) sys_out8(d, x)
+#ifndef UART_REG_ADDR_INTERVAL
 #define UART_REG_ADDR_INTERVAL 1 /* address diff of adjacent regs. */
+#endif
 #else
 #define INBYTE(x) sys_read8(x)
 #define OUTBYTE(x, d) sys_write8(d, x)
+#ifndef UART_REG_ADDR_INTERVAL
 #define UART_REG_ADDR_INTERVAL 4 /* address diff of adjacent regs. */
+#endif
 #endif /* UART_NS16550_ACCESS_IOPORT */
 
 
@@ -252,6 +260,11 @@ static void set_baud_rate(struct device *dev, u32_t baud_rate)
 	if ((baud_rate != 0) && (dev_cfg->sys_clk_freq != 0)) {
 		/* calculate baud rate divisor */
 		divisor = (dev_cfg->sys_clk_freq / baud_rate) >> 4;
+#if defined(CONFIG_SOC_SERIES_CEC)
+		if (dev_cfg->sys_clk_freq == 48000000) {
+			divisor |= 0x8000;
+		}
+#endif
 
 		/* set the DLAB to access the baud rate divisor registers */
 		lcr_cache = INBYTE(LCR(dev));

drivers/spi/CMakeLists.txt

@@ -1,5 +1,6 @@
 zephyr_library()
 
+zephyr_library_sources_ifdef(CONFIG_SPI_CEC_QMSPI	spi_cec_qmspi.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_DW		spi_dw.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_INTEL		spi_intel.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_STM32		spi_ll_stm32.c)

drivers/spi/Kconfig

@@ -160,6 +160,14 @@ config SPI_5_OP_MODES
 
 endif # SPI_5
 
+config SPI_CEC_QMSPI
+	bool
+	prompt "CEC MCU QMSPI controller driver"
+	depends on SPI && SOC_SERIES_CEC
+	default n
+	help
+	  Enable Quad Master SPI support on the CEC series of processors.
+
 config SPI_INTEL
 	bool "Intel SPI controller driver"
 	depends on CPU_MINUTEIA