fix(schematic): Fixes port rendering issue with custom symbols

[Excellencedev]

/claim #1409
/closes #1409

This PR fixes an issue where ports defined inside a custom symbol were not able to be rendered on the PCB side. The issue was that the ports were not able to find the pcb_component_id and source_component_id of the parent chip.

The fix involves traversing the parent chain of the port to find the pcb_component_id and source_component_id from a parent component.

The related test SchematicRect with traces has been updated to include the necessary footprint property, as it is required for the ports to be properly defined and connected in this test case.

Test Logs

USER@DESKTOP-1PHUG1C MINGW64 ~/3D Objects/core (issue-1409)
$ bun test tests/components/primitive-components/schematic-rect-with-traces.test.tsx
bun test v1.2.23 (cf136713)

tests\components\primitive-components\schematic-rect-with-traces.test.tsx:
✓ SchematicRect with traces [906.00ms]

 1 pass
 0 fail
 2 expect() calls
Ran 1 test across 1 file. [2.29s]

USER@DESKTOP-1PHUG1C MINGW64 ~/3D Objects/core (issue-1409)
$

Explanation

The original issue was that ports defined within a custom <symbol> were not being correctly associated with the parent <chip> component's PCB and source information. This was because the port's direct parent was the symbol, which doesn't have this information.

I've resolved this by updating the Port component to traverse up the component hierarchy to find the necessary pcb_component_id and source_component_id from a parent component (like the chip).

It's important to note that for this particular test, the footprint property on the <chip> components is still required. The footprint is what triggers the creation of the underlying PCB and source components that the ports need to associate with. Without it, the test fails because the trace cannot be created.

I have updated the test file to include the necessary footprint properties and the test is now passing.

[vercel]

@Excellencedev is attempting to deploy a commit to the tscircuit Team on Vercel.

A member of the Team first needs to authorize it.

[Excellencedev]

@seveibar Please review

[Excellencedev]

@imrishabh18 Please review