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Achievement: QuickdrawAchievement: Pull Sharkx2

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krushangptl/README.md

🐧 Krushang Patel

About Me

Hello, I'm Krushang Patel, a 4th-year B.Tech student in Electronics and Communication Engineering.

I am a self-taught engineer who loves working with Linux, Python, and Go, diving deep into how things work under the hood. My passion lies in Digital Design, RTL coding, and building robust hardware descriptions that bridge the gap between software and silicon.

I'm on a journey to pursue what I love the most!

Education

Indian Institute of Information Technology, Surat

Bachelor of Technology in Electronics and Communication Engineering

December 2021 to Present

CGPA: 8.21

Thought I was building my resume, ended up building character instead.

Skills

Programming Languages

Python Go Bash
Python Go Bash

Web Development

HTML CSS JavaScript Python SQLite
HTML CSS JS Python SQLite

Tools & Technologies

Linux Git Vim/Neovim GTKWave LTspice
Linux Git Vim GTKWave LTspice

Electronics & Low-Level

VHDL Verilog SystemVerilog ARM Assembly
VHDL Verilog SystemVerilog ARM

Contact Me

Email LinkedIn X Discord

“I can do hard things, I can do whatever I want to, what I need is Time and Momentum.”

Pinned Loading

  1. SysPilot SysPilot Public

    System Health & Automation Daemon

    Python 1

  2. UART_design_verification UART_design_verification Public

    Implementation of UART (Universal Asynchronous Transmitter Receiver) in SystemVerilog.

    SystemVerilog 1

  3. inkflow inkflow Public

    Creating Blogging Website.

    CSS 1

  4. DAC_8_bits DAC_8_bits Public

    Implementation of 8-bit DAC (Digital to Analog Converter) in SystemVerilog.

    SystemVerilog 1

  5. Doc-Scanner-Project Doc-Scanner-Project Public

    A lightweight, end-to-end document scanner built using OpenCV and Tesseract OCR. This project detects documents (like receipts, paper, forms), extracts the perspective-warped version, enhances it, …

    Jupyter Notebook 2

  6. ByteBench ByteBench Public

    Implementation of Synchronous RAM module in VHDL.

    VHDL 1