ByteBench - RAM TESETBENCH PROJECT

Overview

ByteBench is small VHDL project that implements a synchronous RAM module with a testbench to simulate read and write operations. This Project helps in learning:

• VHDL arrays and memory structures
• Synchronous read/write logic
• Writing testbenches for simulations
• Using GHDL and GTKWave for simulation on Linux

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RAM Module Details

• Data width: 8 bits
• Address width: 4 bits -> 16 memory locations
• Inputs:
  • clk - clock
  • rw - read/write control
  • addr - address to read/write
  • data_in - data to write
• Output:
  • data_out - data read from memory

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Simulation Setup on Linux

Install GHDL and GTKWave

sudo apt install ghdl gtkwave

Compile VHDL files

ghdl -a src/ram.vhdl
ghdl -a src/testbench.vhdl

Elaborate the testbench

ghdl -e tb_ram # tb_ram is entity in testbench.vhdl

Run the simulation and generate waveform

ghdl -r tb_ram --vcd=ram.vcd --stop-time=500ns

View waveforms

gtkwave ram.vcd

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by Krushang Patel