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[RISCV][SiFive7] Change Latency of VCIX to the default #106497

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Merged
merged 3 commits into from
Sep 5, 2024
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[RISCV][SiFive7] Change Latency of VCIX to the default #106497

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a3727d4
[RISCV][SiFive7] Change `Latency` of VCIX to the default
michalt Aug 29, 2024
60644c9
fixup! [RISCV][SiFive7] Change `Latency` of VCIX to the default
michalt Aug 29, 2024
400bd24
fixup! [RISCV][SiFive7] Change `Latency` of VCIX to the default
michalt Aug 30, 2024
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11 changes: 7 additions & 4 deletions llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
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Original file line number Diff line number Diff line change
Expand Up @@ -965,15 +965,18 @@ def : InstRW<[WriteIALU], (instrs COPY)>;

// VCIX
//
// In principle we don't know the latency of any VCIX instructions. But instead
// of taking the default of 1, which can lead to issues [1], we assume that they
// have a fairly high latency.
// In principle we don't know the latency of any VCIX instructions (they
// depends on a particular coprocessor implementation). However, the default
// latency of 1 can lead to issues [1]. So instead we set the latency to the
// default provided by `SiFive7GetCyclesDefault`. This is still not accurate
// and can lead to suboptimal codegen, but should hopefully be a better
// starting point.
//
// [1] https://github.com/llvm/llvm-project/issues/83391
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = !mul(Cycles, 10),
let Latency = Cycles,
AcquireAtCycles = [0, 1],
ReleaseAtCycles = [1, !add(1, Cycles)] in {
defm "" : LMULWriteResMX<"WriteVC_V_I", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
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