[microNPU] Improve cascader memory transfer estimates #10508
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Change-Id: Idadc5f354dce42c8dbcdcbe281d324adddb41ba3
jacobbohlin
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areusch,
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icemelon,
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tqchen,
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zhiics
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This was referenced Mar 7, 2022
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@ekalda would be able to take a look here ? |
ekalda
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Mar 9, 2022
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LGTM! Some nits, can be done in a follow up :)
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| read_latency: int = 0, | ||
| write_latency: int = 0, | ||
| burst_length: int = 1, |
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Nit: add these to the docstring as well
| int read_bandwidth; | ||
| /*! \brief The write bandwidth of the region in bytes per cycle */ | ||
| int write_bandwidth; | ||
| /*! \brief The read bandwidth of the region in bytes per cycle */ |
| output_cycles *= reduce(lambda a, b: a * b, output_block, 1) | ||
| output_cycles = int(math.ceil(output_cycles)) | ||
| block_config.append(BlockConfig(output_block, 0, output_cycles)) | ||
| block_config.append(BlockConfig(output_block, output_block, 0, output_cycles)) |
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Maybe use the larger of the input blocks?
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| int read_cycles = bytes_transferred * home_region->read_bandwidth + | ||
| input_configs[i]->GetHomeRegion()->read_latency; |
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nit:
Suggested change
| int read_cycles = bytes_transferred * home_region->read_bandwidth + | |
| input_configs[i]->GetHomeRegion()->read_latency; | |
| int read_cycles = bytes_transferred * home_region->read_bandwidth + | |
| home_region->read_latency; |
manupak
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Mar 14, 2022
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Lets take it in a follow up :)
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Thanks @ekalda @jacobbohlin ! this is merged now. |
pfk-beta
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Apr 11, 2022
Change-Id: Idadc5f354dce42c8dbcdcbe281d324adddb41ba3
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This PR improves the cascader's memory transfer cycle estimates by taking memory burst length and latency into account. Copying tensors between external memories are also more accurately modeled.